Datenblatt-Suchmaschine für elektronische Bauteile
  German  ▼
ALLDATASHEETDE.COM

X  

ISL22449UFV14Z Datenblatt(PDF) 10 Page - Intersil Corporation

Teilenummer ISL22449UFV14Z
Bauteilbeschribung  Low Noise, Low Power, SPI Bus, 128 Taps, Wiper Only
Download  13 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Hersteller  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL22449UFV14Z Datenblatt(HTML) 10 Page - Intersil Corporation

Back Button ISL22449UFV14Z Datasheet HTML 5Page - Intersil Corporation ISL22449UFV14Z Datasheet HTML 6Page - Intersil Corporation ISL22449UFV14Z Datasheet HTML 7Page - Intersil Corporation ISL22449UFV14Z Datasheet HTML 8Page - Intersil Corporation ISL22449UFV14Z Datasheet HTML 9Page - Intersil Corporation ISL22449UFV14Z Datasheet HTML 10Page - Intersil Corporation ISL22449UFV14Z Datasheet HTML 11Page - Intersil Corporation ISL22449UFV14Z Datasheet HTML 12Page - Intersil Corporation ISL22449UFV14Z Datasheet HTML 13Page - Intersil Corporation  
Zoom Inzoom in Zoom Outzoom out
 10 / 13 page
background image
10
FN6333.3
July 17, 2009
SPI Serial Interface
The ISL22449 supports an SPI serial protocol, mode 0. The
device is accessed via the SDI input and SDO output with
data clocked in on the rising edge of SCK, and clocked out
on the falling edge of SCK. CS must be LOW during
communication with the ISL22449. SCK and CS lines are
controlled by the host or master. The ISL22449 operates
only as a slave device.
All communication over the SPI interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
The first byte sent to the ISL22449 from the SPI host is the
Identification Byte. A valid Identification Byte contains 0101
as the four MSBs, with the following four bits set to 0.
TABLE 4. IDENTIFICATION BYTE FORMAT
The next byte sent to the ISL22449 contains the instruction
and register pointer information. The four MSBs are the
instruction and four LSBs are register address (see Table 5).
TABLE 5. IDENTIFICATION BYTE FORMAT
There are only two valid instruction sets:
1011(binary) - is a Read operation
1100(binary) - is a Write operation
Write Operation
A Write operation to the ISL22449 is a three-byte operation. It
requires first, the CS transition from HIGH to LOW, then a valid
Identification Byte, then a valid instruction byte following by
Data Byte is sent to SDI pin. The host terminates the write
operation by pulling the CS pin from LOW to HIGH. For a write
to addresses 0000b to 0011b, the MSB at address 8 (ACR[7])
determines if the Data Byte is to be written to volatile or both
volatile and non-volatile registers. Refer to “Memory
Description” on page 9 and Figure 12.
Device can receive more than one byte of data by auto
incrementing the address after each received byte. Note
after reaching the address 0110b, the internal pointer “rolls
over” to address 0000b.
The internal non-volatile write cycle starts after rising edge of
CS and takes up to 20ms. Thus, non-volatile registers must
be written individually.
Read Operation
A read operation to the ISL22449 is a three-byte operation. It
requires first, the CS transition from HIGH to LOW, then a
valid Identification Byte, then a valid instruction byte
following by “dummy” Data Byte is sent to SDI pin. The SPI
host reads the data from SDO pin on falling edge of SCK.
The host terminates the read operation by pulling the CS pin
from LOW to HIGH (see Figure 13).
The ISL22449 will provide the Data Bytes to the SDO pin as
long as SCK is provided by the host from the registers
indicated by an internal pointer. This pointer initial value is
determined by the register address in the Read operation
instruction, and increments by one during transmission of
each Data Byte. After reaching the memory location 0110b,
the pointer “rolls over” to 0000b, and the device continues to
output the data for each received SCK clock.
In order to read back the non-volatile IVR, it is recommended
that the application reads the ACR first to verify the WIP bit
is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat
its reading sequence again.
TABLE 3.
SHDN pin
SHDN bit
Mode
High
1
Normal operation
Low
1
Shutdown
High
0
Shutdown
Low
0
Shutdown
01010000
(MSB)
(LSB)
76543210
I3
I2
I1
I0
R3
R2
R1
R0
ISL22449


Ähnliche Teilenummer - ISL22449UFV14Z

HerstellerTeilenummerDatenblattBauteilbeschribung
logo
Intersil Corporation
ISL22449UFV14Z INTERSIL-ISL22449UFV14Z Datasheet
356Kb / 12P
   Quad Digitally Controlled Potentiometer
logo
Renesas Technology Corp
ISL22449UFV14Z RENESAS-ISL22449UFV14Z Datasheet
837Kb / 13P
   Quad Digitally Controlled Potentiometer (XDCP™) Low Noise, Low Power, SPI® Bus, 128 Taps, Wiper Only
July 17, 2009
More results

Ähnliche Beschreibung - ISL22449UFV14Z

HerstellerTeilenummerDatenblattBauteilbeschribung
logo
Intersil Corporation
ISL22419 INTERSIL-ISL22419 Datasheet
406Kb / 13P
   Low Noise, Low Power, SPI Bus, 128 Taps, Wiper Only
ISL22426 INTERSIL-ISL22426 Datasheet
627Kb / 15P
   Low Noise, Low Power, SPI Bus, 128 Taps
logo
Renesas Technology Corp
ISL22449 RENESAS-ISL22449 Datasheet
837Kb / 13P
   Quad Digitally Controlled Potentiometer (XDCP™) Low Noise, Low Power, SPI® Bus, 128 Taps, Wiper Only
July 17, 2009
ISL22419 RENESAS-ISL22419 Datasheet
828Kb / 13P
   Single Digitally Controlled Potentiometer (XDCP™) Low Noise, Low Power, SPI® Bus, 128 Taps, Wiper Only
September 8, 2009
ISL22429 RENESAS-ISL22429 Datasheet
832Kb / 13P
   Dual Digitally Controlled Potentiometer (XDCP™) Low Noise, Low Power, SPI®Bus, 128 Taps, Wiper Only
May 28, 2009
ISL22319 RENESAS-ISL22319 Datasheet
873Kb / 13P
   Single Digitally Controlled Potentiometer (XDCP™) Low Noise, Low Power, I2C Bus, 128 Taps, Wiper Only
September 9, 2009
ISL22349 RENESAS-ISL22349 Datasheet
830Kb / 13P
   Quad Digitally Controlled Potentiometers (XDCP™) Low Noise, Low Power, I2C™ Bus, 128 Taps, Wiper Only
May 28, 2009
ISL22329 RENESAS-ISL22329 Datasheet
828Kb / 13P
   Dual Digitally Controlled Potentiometers (XDCP™) Low Noise, Low Power, I2C™ Bus, 128 Taps, Wiper Only
September 4, 2009
logo
Intersil Corporation
ISL22346WMVEP INTERSIL-ISL22346WMVEP Datasheet
99Kb / 3P
   Low Noise, Low Power I2C짰 Bus, 128 Taps
ISL22316WMUEP INTERSIL-ISL22316WMUEP Datasheet
102Kb / 3P
   Low Noise, Low Power I2C짰 Bus, 128 Taps
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13


Datenblatt Download

Go To PDF Page


Link URL




Privatsphäre und Datenschutz
ALLDATASHEETDE.COM
War ALLDATASHEET hilfreich?  [ DONATE ] 

Über Alldatasheet   |   Werbung   |   Kontakt   |   Privatsphäre und Datenschutz   |   Linktausch   |   Hersteller
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com