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74AHCT74PW Datenblatt(PDF) 9 Page - NXP Semiconductors

Teilenummer 74AHCT74PW
Bauteilbeschribung  Dual D-type flip-flop with set and reset; positive-edge trigger
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Hersteller  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

74AHCT74PW Datenblatt(HTML) 9 Page - NXP Semiconductors

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74AHC_AHCT74_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 9 June 2008
9 of 18
NXP Semiconductors
74AHC74; 74AHCT74
Dual D-type flip-flop with set and reset; positive-edge trigger
[1]
Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2]
tpd is the same as tPLH and tPHL.
[3]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(C
L × VCC
2
× f
o) = sum of the outputs.
CPD
power
dissipation
capacitance
fi = 1 MHz; VI = GND to VCC
[3]
-12-
-
-
-
-
pF
74AHCT74; VCC = 4.5 V to 5.5 V
tpd
propagation
delay
nCP to nQ, nQ; see Figure 7
[2]
CL = 15 pF
-
3.3
7.8
1.0
9.0
1.0
10.0
ns
CL = 50 pF
-
4.8
8.8
1.0
10.0
1.0
11.0
ns
nSD, nRD to nQ, nQ;
see Figure 7
CL = 15 pF
-
3.7
10.4
1.0
12.0
1.0
13.0
ns
CL = 50 pF
-
5.3
11.4
1.0
13.0
1.0
14.5
ns
fmax
maximum
frequency
see Figure 7
CL = 15 pF
100
160
-
80
-
80
-
MHz
CL = 50 pF
80
140
-
65
-
65
-
MHz
tW
pulse width
CP HIGH or LOW;
nSD, nRD LOW;
see Figure 7 and 8
5.0
-
-
5.0
-
5.0
-
ns
tsu
set-up time
nD to nCP; see Figure 7
5.0
-
-
5.0
-
5.0
-
ns
th
hold time
nD to nCP; see Figure 7
0-
-
0
-
0
-
ns
trec
recovery
time
nRD to nCP; see Figure 8
3.5
-
-
3.5
-
3.5
-
ns
CPD
power
dissipation
capacitance
fi = 1 MHz; VI = GND to VCC
[3]
-16-
-
-
-
-
pF
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol Parameter
Conditions
25
°C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ[1] Max
Min
Max
Min
Max


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