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74AHCT74BQ Datenblatt(PDF) 4 Page - NXP Semiconductors |
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74AHCT74BQ Datenblatt(HTML) 4 Page - NXP Semiconductors |
4 / 18 page 74AHC_AHCT74_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 9 June 2008 4 of 18 NXP Semiconductors 74AHC74; 74AHCT74 Dual D-type flip-flop with set and reset; positive-edge trigger 5. Pinning information 5.1 Pinning 5.2 Pin description (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input. Fig 5. Pin configuration SO14 and TSSOP14 Fig 6. Pin configuration DHVQFN14 74 1RD VCC 1D 2RD 1CP 2D 1SD 2CP 1Q 2SD 1Q 2Q GND 2Q 001aac449 1 2 3 4 5 6 7 8 10 9 12 11 14 13 001aac450 74 Transparent top view 1Q 2Q 1Q 2SD 1SD 2CP 1CP 2D 1D 2RD 6 9 GND(1) 5 10 4 11 3 12 2 13 terminal 1 index area Table 2. Pin description Symbol Pin Description 1RD 1 asynchronous reset direct input (active LOW) 1D 2 data input 1CP 3 clock input (LOW to HIGH, edge-triggered) 1SD 4 asynchronous set direct input (active LOW) 1Q 5 true flip-flop output 1Q 6 complement flip-flop output GND 7 ground (0 V) 2Q 8 complement flip-flop output 2Q 9 true flip-flop output 2SD 10 asynchronous set direct input (active LOW) 2CP 11 clock input (LOW to HIGH, edge-triggered) 2D 12 data input 2RD 13 asynchronous reset direct input (active LOW) VCC 14 supply voltage |
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Ähnliche Beschreibung - 74AHCT74BQ |
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