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74AHCT259PW Datenblatt(PDF) 11 Page - NXP Semiconductors |
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74AHCT259PW Datenblatt(HTML) 11 Page - NXP Semiconductors |
11 / 17 page 74AHC_AHCT259_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 15 May 2008 11 of 17 NXP Semiconductors 74AHC259; 74AHCT259 8-bit addressable latch Measurement points are given in Table 9. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. Data input to latch enable input set-up and hold times 001aah125 GND GND th tsu th tsu VM VM VM VCC VOH VOL VCC Qn output Q = D Q = D LE input D input Measurement points are given in Table 9. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical voltage output levels that occur with the output load. Fig 10. Address input to latch enable input set-up and hold times 001aah126 VM ADDRESS STABLE VM th tsu VCC GND VCC GND LE input An input Table 9. Measurement points Type Input Output VM VM 74AHC259 0.5 × VCC 0.5 × VCC 74AHCT259 1.5 V 0.5 × VCC |
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