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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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AD21465WBBZ3 Datenblatt(PDF) 1 Page - Analog Devices |
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AD21465WBBZ3 Datenblatt(HTML) 1 Page - Analog Devices |
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1 / 60 page  Preliminary Technical Data SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. SHARC Processor ADSP-21462W/ADSP-21465W/ADSP-21467 Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.3113 ©2008 Analog Devices, Inc. All rights reserved. SUMMARY Note: This datasheet is preliminary. This document contains material that is subject to change without notice. High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Single-instruction, multiple-data (SIMD) computational architecture On-chip memory—5 Mbits of on-chip RAM, 4 Mbits of on-chip ROM Automotive applications—the ADSP-21462W and the ADSP- 21465W are available exclusively as automotive products Code compatible with all other members of the SHARC family The ADSP-21462W/ADSP-21465W/ADSP-21467 are available with unique audiocentric peripherals such as the digital applications interface, DTCP (digital transmission content protection protocol), serial ports, precision clock genera- tors, S/PDIF transceiver, asynchronous sample rate converters, input data port, and more. For complete ordering information, see Automotive Prod- ucts on Page 59 and Ordering Guide on Page 59. Figure 1. Functional Block Diagram 16 DDR2 DRAM CONTROLLER 7 3 DATA EXTERNAL PORT SPI PORT (2) GP TIMERS (2) UART DIGITAL PERIPHERAL INTERFACE SERIAL PORTS (8) INPUT DATA PORT/ PDAP DIGITAL APPLICATIONS INTERFACE IOD(32) ADDR DATA IOA(19) PM DATA BUS DM DATA BUS 32 PM ADDRESS BUS DM ADDRESS BUS 64 PX REGISTER PROCESSING ELEMENT (PEY) PROCESSING ELEMENT (PEX) TIMER INSTRUCTION CACHE 32 x 48-BIT DAG1 CORE PROCESSOR PROGRAM SEQUENCER IOP REGISTER CONTROL STATUS, & DATA BUFFERS DAG2 8 x 4 x 32 I/O PROCESSOR ASRC GPIO 64 32 PRECISION CLOCK GENERATORS (4) TWO WIRE INTERFACE 32 48 S/PDIF (RX/TX) PLL THERMAL DIODE 19 GPIO IRQ/FLAGS MLB LINK PORTS 20 3/5 FLAGS JTAG TEST & EMULATION PWM DAI PINS (20) DPI PINS (14) DDR2 CONTROL 24 ADDRESS DATA ADDRESS 8 DMA ARBITER 8 x 4 x 32 5M BIT RAM 4M BIT ROM FFT FIR IIR ASYNCHRONOUS MEMORY INTERFACE (AMI) 4 S AMI CONTROL 4 BLOCKS OF ON-CHIP MEMORY DTCP 20 14 ACCELERATORS |
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