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LC4131C Datenblatt(PDF) 1 Page - Sanyo Semicon Device |
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LC4131C Datenblatt(HTML) 1 Page - Sanyo Semicon Device |
1 / 7 page Overview The LC4131C is a common driver for large-scale dot matrix LCD panels. It includes a 120-bit bidirectional shift register and 4-level LCD driver circuits. The number of bits can be further increased by using the provided input and output pins to connect multiple LC4131Cs in cascade. The LC4131C and LC4104C form a large-screen LCD panel driver chip set. Features • Fabricated in a CMOS (P-sub) high-voltage process. • LCD drive voltage: 36 V • Logic system power-supply voltage: 2.7 to 5.5 V • fcp max: 2.5 MHz • Slim chip (output pads are concentrated on one of the longer sides) • Bidirectional shift register • The shift register can be split into two 60-bit registers. (Two screens drivable) • DISPOFF function that locks the drive voltages output to the LCD at fixed levels. • Display duty: 1/160 to 1/480 • Appropriate for COG (chip on glass) mounting. (A gold bump structure is adopted in the pad areas.) CMOS IC Ordering number : EN*5953 40398RM (OT) No. 5953-1/7 SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN LCD Dot Matrix Common Driver for STN Displays LC4131C Specifications The electrical characteristics values shown below are for devices encapsulated in the Sanyo standard PGA-208 package. Absolute Maximum Ratings at VSS = 0 V Note: 1. LOAD, RS/LS, DISP, DF, DIO1, DIO120, DMIN and MODE 2. The voltages V0, V1, V4, and V5 must obey the relationships VEE ≥ V0 ≥ V1 ≥ VEE – 7 V, and 7 V ≥ V4 ≥ V5 ≥ VSSH. Allowable Operating Ranges at VSS = 0 V, Ta = –20 to +75°C Note: 1. LOAD, RS/LS, DISP, DF, DIO1, DIO120, DMIN and MODE 2. The voltages V0, V1, V4, and V5 must obey the relationships VEE ≥ V0 ≥ V1 ≥ VEE – 7 V, and 7 V ≥ V4 ≥ V5 ≥ VSSH. When turning on the power supplies, first turn on the logic system power supply and then turn on the high-voltage system power supply; alternatively, turn both on at the same time. When turning off the power supplies, first turn off the high-voltage system power supply and then turn off the logic system power supply; alternatively, turn both off at the same time. Ratings Parameter Symbol Applicable pins min typ max Unit VDD max VDD –0.3 7.0 V Supply voltage VEE max VEE –0.3 40.0 V VSSH max VSSH –0.3 0.3 V VIN *1 –0.3 VDD + 0.3 V Input voltage V0, V1 V0, V1 *2 VEE – 7.0 VEE + 0.3 V V4 V4 *2 –0.3 VSS + 7.0 V V5 V5 *2 –0.3 +0.3 V Operating temperature Topr –20 +75 °C Storage temperature Tstg –55 +125 °C Ratings Parameter Symbol Applicable pins min typ max Unit VDD VDD 2.7 5.5 V Supply voltage VEE VEE 14 36 V VSSH VSSH 0V Input high-level voltage VIH *1 0.8 × VDD VDD V Input low-level voltage VIL *1 0 0.2 × VDD V V0, V1 V0, V1 *2 VEE – 7.0 VEE V Input voltage V4 V4 *2 0 VSSH + 7.0 V V5 V5 *2 0V Preliminary |
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