Serial Data Output

1. When CL is stopped at the low level

2. When CL is stopped at the high level

• CCB address...............43H

• KD1 to KD30 .............Key data

• SA...............................Sleep acknowledge data

Note: If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep

acknowledge data (SA) will be invalid.

Output Data

1. KD1 to KD30: Key data

When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and the KI1 to KI5 input pins and

one of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the

relationship between those pins and the key data bits.

When the KS1/S23 and KS2/S24 output pins are selected to be segment outputs by control data bits K0 and K1 and a

key matrix of up to 20 keys is formed using the KS3 to KS6 output pins and the KI1 to KI5 input pins, the KD1 to

KD10 key data bits will be set to 0.

2. SA: Sleep acknowledge data

This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial data

is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in sleep

mode and 0 in normal mode.

No. 6860-11/26

LC75864E, 75864W

KI1

KI2

KI3

KI4

KI5

KS1/S23

KD1

KD2

KD3

KD4

KD5

KS2/S24

KD6

KD7

KD8

KD9

KD10

KS3

KD11

KD12

KD13

KD14

KD15

KS4

KD16

KD17

KD18

KD19

KD20

KS5

KD21

KD22

KD23

KD24

KD25

KS6

KD26

KD27

KD28

KD29

KD30

CE

CL

DI

DO

Output data

X: don’t care

1

1

0

0

0

0

1

0

B0

B1

B2

B3

A0

A1

A2

A3

KD2

KD27 KD28 KD29 KD30

SA

KD1

X

CE

CL

DI

DO

Output data

X: don’t care

1

1

0

0

0

0

1

0

B0

B1

B2

B3

A0

A1

A2

A3

KD3

KD28 KD29 KD30

SA

X

KD2

KD1

X

Note: B0 to B3, A0 to A3 ... CCB address

Note: B0 to B3, A0 to A3 ... CCB address