Datenblatt-Suchmaschine für elektronische Bauteile |
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LC78601E Datenblatt(PDF) 7 Page - Sanyo Semicon Device |
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LC78601E Datenblatt(HTML) 7 Page - Sanyo Semicon Device |
7 / 11 page No. 6020-7/11 LC78601E Pin No. Pin I/O Function Pin state during reset Monitor for C1, C2, single, and double error corrections. 49 EFLG O (Note that this output is only provided in test mode. This pin outputs a low level during normal Low output mode operation.) Outputs a 7.35 kHz synchronizing signal that is generated by dividing the crystal oscillator output. 50 FSX O (Note that this output is only provided in test mode. This pin outputs a low level during normal Low output mode operation.) 51 *AMUTE O Audio mute output signal Low output 52 REMOTE I Remote controller signal input — Remote controller identifier input (2). This pin functions as an output pin set to the low level 53 RMTSL2 I/O during resets (when the *RES pin is low) and for a few milliseconds after the *RES pin Low output switches to the high level. Therefore, applications that will set this pin high must connect an external pull-up resistor to this pin. 54 LCHO O Left channel D/A converter output Undefined 55 L/RVDD — D/A converter power supply — 56 L/RVSS — D/A converter ground. This pin must be connected to 0 V. — 57 RCHO O Right channel D/A converter output Undefined 58 CLOSE I Close switch detection input. A pull-up resistor is built in. — 59 RMTSL1 I Remote controller identifier input (1). A pull-up resistor is built in. — 60 XOUT O Connections for a 16.9344 crystal element Clock output 61 XIN I — 62 XVDD — Crystal oscillator circuit power supply — 63 *RES I IC reset input. Applications must set this pin low temporarily when power is first applied. — 64 DRF I DRF input. (Connected when an LA9250M is used.) — Continued from preceding page. Note: The same potential must be connected to all the power supply pins (VDD, VVDD, L/RVDD, and XVDD). |
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