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STK12C68-SF25I Datenblatt(PDF) 1 Page - Cypress Semiconductor |
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STK12C68-SF25I Datenblatt(HTML) 1 Page - Cypress Semiconductor |
1 / 24 page STK12C68 64 Kbit (8K x 8) AutoStore nvSRAM Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-51027 Rev. *C Revised March 7, 2011 Features ■ 25 ns, 35 ns, and 45 ns access times ■ Hands off automatic STORE on power down with external 68 µF capacitor ■ STORE to QuantumTrap nonvolatile elements is initiated by software, hardware, or AutoStore on power down ■ RECALL to SRAM initiated by software or power up ■ Unlimited Read, Write, and Recall cycles ■ 1,000,000 STORE cycles to QuantumTrap ■ 100 year data retention to QuantumTrap ■ Single 5V+10% operation ■ Commercial and industrial temperatures ■ 228-pin (330mil) SOIC, 28-pin (300mil) PDIP, 28-pin (600mil) PDIP packages ■ 28-pin (300 mil) CDIP and 28-pad (350 mil) LCC packages ■ RoHS compliance Functional Description The Cypress STK12C68 is a fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. A hardware STORE is initiated with the HSB pin. STORE/ RECALL CONTROL POWER CONTROL SOFTWARE DETECT STATIC RAM ARRAY 128 X 512 Quantum Trap 128 X 512 STORE RECALL COLUMN I/O COLUMN DEC OE CE WE HSB VCC VCAP A0 - A12 A0 A1 A2 A3 A4 A10 A5 A6 A7 A8 A9 A11 A12 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Logic Block Diagram [+] Feedback |
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