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TC1762 Datenblatt(PDF) 7 Page - Infineon Technologies AG |
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TC1762 Datenblatt(HTML) 7 Page - Infineon Technologies AG |
7 / 114 page TC1762 Summary of Features Preliminary Data Sheet 3 V1.0, 2008-04 1 Summary of Features The TC1762 has the following features: • High-performance 32-bit super-scaler TriCore v1.3 CPU with 4-stage pipeline – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Single precision Floating Point Unit (FPU) – 66 or 80 MHz operation at full temperature range • Multiple on-chip memories – 32 Kbyte Local Data Memory (SRAM) – 4 Kbyte Overlay Memory – 8 Kbyte Scratch-Pad RAM (SPRAM) – 8 Kbyte Instruction Cache (ICACHE) – 1024 Kbyte Flash Memory – 16 Kbyte Data Flash (2 Kbyte EEPROM emulation) – 16 Kbyte Boot ROM • 8-channel DMA Controller • Fast-response interrupt system with 255 hardware priority arbitration levels serviced by CPU • High-performance on-chip bus structure – 64-bit Local Memory Bus (LMB) to Flash memory – System Peripheral Bus (SPB) for interconnections of functional units • Versatile on-chip Peripheral Units – Two Asynchronous/Synchronous Serial Channels (ASCs) with baudrate generator, parity, framing and overrun error detection – One High Speed Synchronous Serial Channel (SSC) with programmable data length and shift direction – One Micro Second Bus (MSC) interface for serial port expansion to external power devices – One high-speed Micro Link Interface (MLI) for serial inter-processor communication – One MultiCAN Module with two CAN nodes and 64 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer – One General Purpose Timer Array Module (GPTA) with a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management – One 16-channel Analog-to-Digital Converter unit (ADC) with selectable 8-bit, 10- bit, or 12-bit, supporting 32 input channels – One 2-channel Fast Analog-to-Digital Converter unit (FADC) with concatenated comb filters for hardware data reduction: supporting 10-bit resolution, with minimum conversion time of 262.5ns (@ 80 MHz) or 318.2ns (@ 66 MHz) |
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Ähnliche Beschreibung - TC1762 |
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