IDT5V925BQGI REVISION B JANUARY 21, 2011

10

©2011 Integrated Device Technology, Inc.

IDT5V925BI Data Sheet

PROGRAMMABLE LVCMOS/LVTTL CLOCK GENERATOR

Schematic Examples

Figures 4A and 4B show an examples of IDT5V925BI application

load capacitance, C1 = 27pF and C2 = 27pF are recommended for

frequency accuracy. Depending on the parasitics of the printed circuit

board layout, these values might require a slight adjustment to

optimize the frequency accuracy. Crystals with other load

capacitance specifications can be used. This will required adjusting

C1 and C2. In Figure 4B example, the LVCMOS clock reference input

is used.

As with any high speed analog circuitry, the power supply pins are

vulnerable to noise. To achieve optimum jitter performance, power

supply isolation is required. The IDT5V925BI provides separate

power supplies to isolate from coupling into the internal PLL.

Figure 4A. IDT5V925BI Application Schematic with Crystal Input Reference

R4

100

Set Logic

Input to

'0'

C5

10uF

1 8 p F

Please short the

CLKIN pin and X2

pin for the

crystal input

option.

RU1

1K

R1

33

S1

RD2

1K

R3

100

3.3V

R2

33

LVCMOS

RU2

Not Install

To Logic

Input

pins

S2

/OE

Logic Control Input Examples

C8

10uF

Q/N

VDD

Unused output can be left floating. There should

no trace attached to unused output. Device

characterized with all outputs terminated.

VDDQ=3.3V

LVCMOS

VDD=3.3V

C7

0.1uF

C4

0.1uF

VDDQ

Zo = 50 Ohm

RD1

Not Install

VDDQ

Zo = 50 Ohm

C6

0.1uF

XTAL_IN

X1

25MHz

Set Logic

Input to

'1'

U1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

S1

S0

GNDQ

VDDQ

X1

X2

CLKIN

FB

/OE

GND

Q/N

Q0

Q1

Q2

GND

VDD

VDD

C1

27pF

XTAL_OUT

C2

27pF

Q1

Optional Termination

Q0

BLM18BB221SN1

Ferrite Bead

1

2

VDD

To Logic

Input

pins

3.3V

C3

0.1uF

BLM18BB221SN2

Ferrite Bead

1

2

Q2