Datenblatt-Suchmaschine für elektronische Bauteile
  German  ▼
ALLDATASHEETDE.COM

X  

ADF4360-4BCPRL7 Datenblatt(PDF) 10 Page - Analog Devices

Teilenummer ADF4360-4BCPRL7
Bauteilbeschribung  Integrated Synthesizer and VCO
Download  24 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Hersteller  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADF4360-4BCPRL7 Datenblatt(HTML) 10 Page - Analog Devices

Back Button ADF4360-4BCPRL7 Datasheet HTML 6Page - Analog Devices ADF4360-4BCPRL7 Datasheet HTML 7Page - Analog Devices ADF4360-4BCPRL7 Datasheet HTML 8Page - Analog Devices ADF4360-4BCPRL7 Datasheet HTML 9Page - Analog Devices ADF4360-4BCPRL7 Datasheet HTML 10Page - Analog Devices ADF4360-4BCPRL7 Datasheet HTML 11Page - Analog Devices ADF4360-4BCPRL7 Datasheet HTML 12Page - Analog Devices ADF4360-4BCPRL7 Datasheet HTML 13Page - Analog Devices ADF4360-4BCPRL7 Datasheet HTML 14Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 24 page
background image
ADF4360-4
Rev. A | Page 10 of 24
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4360 family allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. The full truth table is shown in Table 7. Figure 13 shows
the MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital and analog. Digital lock detect is active high. When LDP
in the R counter latch is set to 0, digital lock detect is set high
when the phase error on three consecutive phase detector cycles
is less than 15 ns.
With LDP set to 1, five consecutive cycles of less than 15 ns
phase error are required to set the lock detect. It stays set high
until a phase error greater than 25 ns is detected on any
subsequent PD cycle.
The N-channel open-drain analog lock detect should be oper-
ated with an external pull-up resistor of 10 kΩ nominal. When a
lock has been detected, the output is high with narrow low-
going pulses.
R COUNTER OUTPUT
N COUNTER OUTPUT
DIGITAL LOCK DETECT
DGND
CONTROL
MUX
MUXOUT
DVDD
ANALOG LOCK DETECT
SDOUT
Figure 13. MUXOUT Circuit
INPUT SHIFT REGISTER
The ADF4360 family’s digital section includes a 24-bit input
shift register, a 14-bit R counter, and an 18-bit N counter,
comprised of a 5-bit A counter and a 13-bit B counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. The two LSBs are DB1 and
DB0, as shown in Figure 2.
The truth table for these bits is shown in Table 5. Table 6 shows
a summary of how the latches are programmed. Note that the
test mode latch is used for factory testing and should not be
programmed by the user.
Table 5. C2 and C1 Truth Table
Control Bits
C2
C1
Data Latch
0
0
Control Latch
0
1
R Counter
1
0
N Counter (A and B)
1
1
Test Mode Latch
VCO
The VCO core in the ADF4360 family uses eight overlapping
bands, as shown in Figure 14, to allow a wide frequency range to
be covered without a large VCO sensitivity (KV) and resultant
poor phase noise and spurious performance.
The correct band is chosen automatically by the band select
logic at power-up or whenever the N counter latch is updated. It
is important that the correct write sequence be followed at
power-up. This sequence is
1.
R counter latch
2.
Control latch
3.
N counter latch
During band select, which takes five PFD cycles, the VCO VTUNE
is disconnected from the output of the loop filter and connected
to an internal reference voltage.
0
1350
1450
1550
1650
1750
1850
1250
1950
0.5
1.0
1.5
2.0
2.5
3.0
3.5
FREQUENCY (MHz)
Figure 14. Frequency vs. VTUNE, ADF4360-4
The R counter output is used as the clock for the band select logic
and should not exceed 1 MHz. A programmable divider is provided
at the R counter input to allow division by 1, 2, 4, or 8 and is con-
trolled by Bits BSC1 and BSC2 in the R counter latch.Where the
required PFD frequency exceeds 1 MHz, the divide ratio should be
set to allow enough time for correct band selection.
After band select, normal PLL action resumes. The nominal value
of KV is 50 MHz/V or 25 MHz/V, if divide-by-2 operation has been
selected (by programming DIV2 [DB22] high in the N counter
latch). The ADF4360 family contains linearization circuitry to
minimize any variation of the product of ICP and KV.


Ähnliche Teilenummer - ADF4360-4BCPRL7

HerstellerTeilenummerDatenblattBauteilbeschribung
logo
Analog Devices
ADF4360-4BCP AD-ADF4360-4BCP Datasheet
336Kb / 20P
   Integrated Synthesizer and VCO
REV. B
ADF4360-4BCPZ AD-ADF4360-4BCPZ Datasheet
394Kb / 24P
   Integrated Synthesizer and VCO
ADF4360-4BCPZRL AD-ADF4360-4BCPZRL Datasheet
394Kb / 24P
   Integrated Synthesizer and VCO
ADF4360-4BCPZRL7 AD-ADF4360-4BCPZRL7 Datasheet
394Kb / 24P
   Integrated Synthesizer and VCO
More results

Ähnliche Beschreibung - ADF4360-4BCPRL7

HerstellerTeilenummerDatenblattBauteilbeschribung
logo
Analog Devices
ADF4360-8 AD-ADF4360-8 Datasheet
570Kb / 24P
   Integrated Synthesizer and VCO
REV. A
ADF4360-0 AD-ADF4360-0 Datasheet
315Kb / 24P
   Integrated Synthesizer and VCO
REV. B
ADF4360-5 AD-ADF4360-5 Datasheet
480Kb / 24P
   Integrated Synthesizer and VCO
REV. A
ADF4360-7 AD-ADF4360-7 Datasheet
336Kb / 28P
   Integrated Synthesizer and VCO
REV. B
ADF4360-2 AD-ADF4360-2 Datasheet
336Kb / 20P
   Integrated Synthesizer and VCO
REV. B
ADF4360-8 AD-ADF4360-8_15 Datasheet
716Kb / 24P
   Integrated Synthesizer and VCO
REV. C
ADF4360-2 AD-ADF4360-2_15 Datasheet
589Kb / 24P
   Integrated Synthesizer and VCO
REV. C
ADF4360-1 AD-ADF4360-1_16 Datasheet
377Kb / 24P
   Integrated Synthesizer and VCO
ADF4360-4 AD-ADF4360-4_16 Datasheet
394Kb / 24P
   Integrated Synthesizer and VCO
ADF4360-6 AD-ADF4360-6_16 Datasheet
389Kb / 24P
   Integrated Synthesizer and VCO
ADF4360-0 AD-ADF4360-0_16 Datasheet
366Kb / 24P
   Integrated Synthesizer and VCO
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24


Datenblatt Download

Go To PDF Page


Link URL




Privatsphäre und Datenschutz
ALLDATASHEETDE.COM
War ALLDATASHEET hilfreich?  [ DONATE ] 

Über Alldatasheet   |   Werbung   |   Kontakt   |   Privatsphäre und Datenschutz   |   Linktausch   |   Hersteller
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com