Datenblatt-Suchmaschine für elektronische Bauteile |
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ADF4360-9BCPZRL Datenblatt(PDF) 11 Page - Analog Devices |
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ADF4360-9BCPZRL Datenblatt(HTML) 11 Page - Analog Devices |
11 / 24 page Data Sheet ADF4360-9 Rev. B | Page 11 of 24 The truth table for these bits is shown in Table 5. Figure 22 shows a summary of how the latches are programmed. Note that the test modes latch is used for factory testing and should not be programmed by the user. Table 5. C2 and C1 Truth Table Control Bits C2 C1 Data Latch 0 0 Control 0 1 R Counter 1 0 N Counter (B) 1 1 Test Modes VCO The VCO core in the ADF4360 family uses eight overlapping bands, as shown in Figure 18, to allow a wide frequency range to be covered without a large VCO sensitivity (KV) and resultant poor phase noise and spurious performance. The correct band is chosen automatically by the band select logic at power-up or whenever the N counter latch is updated. It is important that the correct write sequence be followed at power-up. The correct write sequence is as follows: 1. R Counter Latch 2. Control Latch 3. N Counter Latch During band selection, which takes five PFD cycles, the VCO VTUNE is disconnected from the output of the loop filter and connected to an internal reference voltage. 0 1.0 0.5 2.5 2.0 1.5 3.5 3.0 80 85 90 100 95 105 115 110 FREQUENCY (MHz) Figure 18. VTUNE, ADF4360-9, L1 and L2 = 270 nH vs. Frequency The R counter output is used as the clock for the band select logic and should not exceed 1 MHz. A programmable divider is provided at the R counter input to allow division by 1, 2, 4, or 8 and is controlled by the BSC1 bit and the BSC2 bit in the R counter latch. Where the required PFD frequency exceeds 1 MHz, the divide ratio should be set to allow enough time for correct band selection. For many applications, it is usually best to set this to 8. After band selection, normal PLL action resumes. The value of KV is determined by the value of the inductors used (see the Choosing the Correct Inductance Value section). The ADF4360 family contains linearization circuitry to minimize any variation of the product of ICP and KV. The operating current in the VCO core is programmable in four steps: 2.5 mA, 5 mA, 7.5 mA, and 10 mA. This is controlled by the PC1 bit and the PC2 bit in the control latch. It is strongly recommended that only the 5 mA setting be used. However, in applications requiring a low VCO frequency, the high temperature coefficient of some inductors may lead to the VCO tuning voltage varying as temperature changes. The 7.5 mA VCO core power setting shows less tuning voltage variation over temperature in these applications and can be used, provided that 240 Ω resistors are used in parallel with Pin 9 and Pin 10, instead of the default 470 Ω. |
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Ähnliche Beschreibung - ADF4360-9BCPZRL |
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