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Electrical Characteristics

Timing Requirements

SN74SSTV32867-EP

26-BIT REGISTERED BUFFER

WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS

SCES664 – SEPTEMBER 2006

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

UNIT

2.3 V

–1.5

V

2.3 V to 2.7 V

V

2.3 V

1.7

2.3 V to 2.7 V

0.2

V

2.3 V

0.45

All inputs

2.7 V

±5

µA

Static standby

RESET = GND

40

µA

2.7 V

Static operating

95

mA

Dynamic

operating –

44

µA/MHZ

CLK and CLK switching,

clock only

50% duty cycle

2.5 V

Dynamic

CLK and CLK switching,

µA/clock

operating –

50% duty cycle,

5

MHz/

per each data

One data input switching at

D input

input

one-half clock frequency,

50% duty cycle

Data inputs

3.5

CLK, CLK

2.5 V

4.5

pF

RESET

5

(1)

(2)

Measured with 50-MHz input frequency

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)

± 0.2 V

UNIT

MIN

TYP

MAX

Clock frequency

200

MHz

Pulse duration

CLK, CLK high or low

2.5

ns

22

ns

22

ns

1.0

Data before CLK

↑,

Setup time

ns

CLK

↓

1.5

1.0

Hold time

Data after CLK

↑, CLK↓

ns

1.5

(1)

(2)

(3)

Data signal input slew rate

≥ 1 V/ns

(4)

CLK, CLK input slew rates are

≥ 1 V/ns.

(5)

Data signal input slew rate

≥ 0.5 V/ns and < 1 V/ns

4

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