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SN74V283-EP Datenblatt(PDF) 3 Page - Texas Instruments |
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SN74V283-EP Datenblatt(HTML) 3 Page - Texas Instruments |
3 / 49 page SN74V263-EP, SN74V273-EP, SN74V283-EP, SN74V293-EP 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS695A – JUNE 2003 – REVISED JUNE 2003 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional block diagram Write-Control Logic RAM Array 8192 × 18 or 16384 × 9 16384 × 18 or 32768 × 9 32768 × 18 or 65536 × 9 65536 × 18 or 131072 × 9 Offset Register Input Register Flag Logic Read Pointer Read-Control Logic Output Register Write Pointer Control Logic Reset Logic BE IP MRS WEN WCLK D0–Dn ( ×9 or ×18) SEN HF PAE EF/OR PAF FF/IR Q0–Qn ( ×9 or ×18) OE REN RCLK Bus Configuration IW OW PRS LD FSEL1 FSEL0 PFM FWFT/SI RM RT description/ordering information (continued) The frequencies of both the RCLK and the WCLK signals can vary from 0 to fMAX, with complete independence. There are no restrictions on the frequency of one clock input with respect to the other. There are two possible timing modes of operation with these devices: first-word fall-through (FWFT) mode and standard mode. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. REN need not be asserted for accessing the first word. However, subsequent words written to the FIFO do require a low on REN for access. The state of the FWFT/SI input during master reset determines the timing mode in use. In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN and enabling a rising RCLK edge, shifts the word from internal memory to the data output lines. For applications requiring more data-storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e., the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required. |
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