Datenblatt-Suchmaschine für elektronische Bauteile |
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SM320C6712C-EP Datenblatt(PDF) 2 Page - Texas Instruments |
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SM320C6712C-EP Datenblatt(HTML) 2 Page - Texas Instruments |
2 / 109 page SM320C6712EP, SM320C6712CEP, SM320C6712DEP FLOATINGPOINT DIGITAL SIGNAL PROCESSORS SGUS055 − SEPTEMBER 2004 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Table of Contents EMIF device speed 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIF big endian mode correctness [C6712D only] 60 . . . bootmode 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings over operating case temperature range 61 . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions 62 . . . . . . . . . . . . . . . . electrical characteristics over recommended ranges of supply voltage and operating case temperature 63 . parameter measurement information 64 . . . . . . . . . . . . . . . signal transition levels 65 . . . . . . . . . . . . . . . . . . . . . . . . . . timing parameters and board routing analysis 65 . . . . . . input and output clocks 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . asynchronous memory timing 72 . . . . . . . . . . . . . . . . . . . . . synchronous-burst memory timing 75 . . . . . . . . . . . . . . . . . synchronous DRAM timing 77 . . . . . . . . . . . . . . . . . . . . . . . . HOLD/HOLDA timing 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUSREQ timing 84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset timing [C6712] 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset timing [C6712C/C6712D] 87 . . . . . . . . . . . . . . . . . . . . external interrupt timing 89 . . . . . . . . . . . . . . . . . . . . . . . . . . multichannel buffered serial port timing 90 . . . . . . . . . . . . . timer timing 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general-purpose input/output (GPIO) port timing [C6712C/C6712D only] 105 . . . . . . . . . . . . . . . . . . . . . JTAG test-port timing 106 . . . . . . . . . . . . . . . . . . . . . . . . . . . mechanical data [C6712 only] 107 . . . . . . . . . . . . . . . . . . . . mechanical data [C6712C/C6712D only] 108 . . . . . . . . . . . GFN BGA package (bottom view) [C6712 only] 3 . . . . . . . . . . GDP BGA package (bottom view) [C6712C/12D only] 3 . . . . description 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device characteristics 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device compatibility 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . functional block and CPU (DSP core) diagram 7 . . . . . . . . . . . CPU (DSP core) description 8 . . . . . . . . . . . . . . . . . . . . . . . . . . memory map summary 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peripheral register descriptions 11 . . . . . . . . . . . . . . . . . . . . . . . signal groups description 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . device configurations 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . terminal functions 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . development support 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . documentation support 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU CSR register description 37 . . . . . . . . . . . . . . . . . . . . . . . . cache configuration (CCFG) register description (12D) 39 . . . interrupt sources and interrupt selector [C6712 only] 40 . . . . interrupt sources and interrupt selector [12C/12D only] 41 . . EDMA channel synchronization events [C6712 only] 42 . . . . EDMA module and EDMA selector [12C/12D only] 43 . . . . . . clock PLL [C6712 only] 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL and PLL controller [C6712C/C6712D only] 47 . . . . . . . . . general-purpose input/output (GPIO) 54 . . . . . . . . . . . . . . . . . . power-down mode logic 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply sequencing 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply decoupling 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE 1149.1 JTAG compatibility statement 59 . . . . . . . . . . . . . |
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