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SM34020AGBS40 Datenblatt(PDF) 10 Page - Texas Instruments

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Teilenummer SM34020AGBS40
Bauteilbeschribung  GRAPHICS SYSTEM PROCESSOR
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SM34020AGBS40 Datenblatt(HTML) 10 Page - Texas Instruments

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SM34020A
GRAPHICS SYSTEM PROCESSOR
SGUS057 − FEBRUARY 2005
10
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
transparency
Transparency is a mechanism that allows the surrounding pixels in an array to be specified as invisible. This
is useful for ensuring that only the object and not the rectangle surrounding it are written to the display. The
SM34020A provides four transparency modes:
D No transparency
D Transparency on result equal zero
D Transparency on source equal COLOR0
D Transparency on destination equal COLOR0
D Refer to the TMS34020 User’s Guide for more information.
I/O registers
The SM34020A contains an on-chip block of sixty-four 16-bit locations (mapped into the SM34020A memory
address space) that are used for I/O control registers. Eight of these are used by the host interface logic and
are not available to the user. Forty-seven I/O registers control parameters necessary to configure the operation
and report status of the following interfaces:
D Host interface
D Local memory
D Video timing
D Screen refresh
D External interrupts
D Internal interrupts
host interface registers
The host interface registers (HSTDATA, HSTADRL, HSTADRH, HSTCTLL, and HSTCTLH) are provided to
facilitate communications between the SM34020A and a host processor and maintain compatibility with the
SMJ34010. The registers are mapped into five of the I/O locations accessible to the SM34020A.
Two of these registers (HSTCTLL and HSTCTLH) are used to provide control by the host. This control consists
of the passing of interrupt requests, flushing the instruction cache, halting the SM34020A, transmitting a
non-maskable interrupt request to the SM34020A, enabling emulation interrupts, and setting host access
modes and configurations.
The other three registers are simple read/write registers to allow the SM34020A software to leave addresses
for the host at a known location and allow compatibility with some SMJ34010 software.
memory interface control registers
Some of the I/O registers are used to control various local memory interface functions, including:
D Frequency of DRAM refresh cycles
D Masking (read/write protection) of individual color planes
D DRAM row/column addressing configuration
D Accessing mode (big endian/little endian)
D Bus fault and retry recovery
video timing and screen refresh
Twenty-eight I/O registers are dedicated to video timing and screen refresh functions. The SM34020A can be
configured to drive composite sync or separate sync displays.
In composite sync mode, the SM34020A can be set to extract VSYNC and HSYNC from an external CSYNC
or it can be used to generate CSYNC from separate VSYNC and HSYNC inputs. Internally, the SM34020A can
be set to preset the horizontal and vertical counts on receipt of an external sync signal. This allows
compensation for any combination of internal and external delays that occur in the video synchronization
process.
The
Not Recommended for New Designs


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