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SM320C32PCMM50EP Datenblatt(PDF) 2 Page - Texas Instruments |
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SM320C32PCMM50EP Datenblatt(HTML) 2 Page - Texas Instruments |
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2 / 44 page  SM320C32EP DIGITAL SIGNAL PROCESSOR SGUS038 − AUGUST 2002 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 description The SM320C32-EP is a member of the 320C3x generation of digital signal processors from Texas Instruments. The SM320C32-EP is an enhanced 32-bit floating-point processor manufactured in 0.7- µm triple-level-metal CMOS technology. The enhancements to the 320C3x architecture include a variable-width external-memory interface, faster instruction cycle time, power-down modes, two-channel DMA coprocessor with configurable priorities, flexible bootloader, relocatable interrupt-vector table, and edge- or level-triggered interrupts. The internal busing and special digital signal processing instruction set of the SM320C32-EP have the speed and flexibility to execute up to 50 million floating-point operations per second (MFLOPS). The SM320C32-EP optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip. For additional information when designing for cold temperature operation, please see Texas Instruments application report 320C3x, 320C4x and 320MCM42x Power-up Sensitivity at Cold Temperature, literature number SGUA001. part order information DEVICE TECHNOLOGY POWER SUPPLY OPERATING FREQUENCY PACKAGE TYPE PROCESSING LEVEL SM320C32PCMM50EP 0.65- µm CMOS 5 V ± 5% 50 MHz Plastic 144-lead quad flatpack EP SM320C32PCMM60EP 0.65- µm CMOS 5 V ± 5% 60 MHz Plastic 144-lead quad flatpack EP |
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