SMJ320C50/SMQ320C50

DIGITAL SIGNAL PROCESSOR

SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001

7

POST OFFICE BOX 1443

Terminal Functions (Continued)

TERMINAL

DESCRIPTION

NAME

DESCRIPTION

MEMORY CONTROL SIGNALS (CONTINUED)

WE

O/Z

Write enable. The falling edge indicates that the device is driving the external data bus (D15--D0). Data can be

latched by an external device on the rising edge of WE. This signal is active on all external program, data, and I/O

writes. WE is in the high-impedance state in hold mode or when OFF is active (low).

MULTIPROCESSING SIGNALS

HOLD

I

Hold. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the C50,

these lines go to the high-impedance state.

HOLDA

O/Z

Hold acknowledge. HOLDA indicates to the external circuitry that the processor is in a hold state and that the

address, data, and memory control lines are in the high-impedance state so that they are available to the external

circuitry for access to local memory. This signal also goes to the high-impedance state when OFF is active (low).

BR

I/O/Z

Bus request. BR is asserted during access of external global data memory space. READY is asserted when the

global data memory is available for the bus transaction. BR can be used to extend the data memory address space

by up to 32K words. BR goes to the high-impedance state when OFF is active low. BR is used in external DMA access

of the on-chip single-access RAM. While HOLDA is active (low), BR is externally driven (low) to request access to

the on-chip single-access RAM.

IAQ

O/Z

Instruction acquisition. Asserted (active) when there is an instruction address on the address bus; goes into the

high-impedance state when OFF is active (low). IAQ is also used in external DMA access of the on-chip

single-access RAM. While HOLDA is active (low), IAQ acknowledges the BR request for access of the on-chip

single-access RAM and stops indicating instruction acquisition.

BIO

I

Branch control. BIO samples as the BIO condition and, if it is low, causes the device to execute the conditional

instruction. BIO must be active during the fetch of the conditional instruction.

XF

O/Z

External flag (latched software-programmable signal). Set high or low by a specific instruction or by loading status

register 1 (ST1). Used for signaling other processors in multiprocessor configurations or as a general-purpose

output. XF goes to the high-impedance state when OFF is active (low) and is set high at reset.

IACK

O/Z

Interrupt acknowledge. Indicates receipt of an interrupt and that the program counter is fetching the interrupt vector

location designated by A15--A0. IACK goes to the high-impedance state when OFF is active (low).

INITIALIZATION, INTERRUPT, AND RESET OPERATIONS

INT4

INT3

INT2

INT1

I

External interrupts. INT1--INT4 are prioritized and maskable by the interrupt mask register (IMR) and interrupt mode

bit (INTM, bit 9 of status register 0). These signals can be polled and reset by using the interrupt flag register.

NMI

I

Nonmaskable interrupt. NMI is the external interrupt that cannot be masked via INTM or IMR. When NMI is activated,

the processor traps to the appropriate vector location.

RS

I

Reset. RS causes the device to terminate execution and forces the program counter to zero. When RS is brought

to a high level, execution begins at location zero of program memory.

MP/MC

I

Microprocessor/microcomputer select. If active (low) at reset (microcomputer mode), the signal causes the internal

program ROM to be mapped into program memory space. In the microprocessor mode, all program memory is

mapped externally. This signal is sampled only during reset, and the mode that is set at reset can be overridden via

the software control bit MP/MC in the PMST register.

OSCILLATOR/TIMER SIGNALS

CLKOUT1

O/Z

Master clock (or CLKIN2 frequency). CLKOUT1 cycles at the machine-cycle rate of the CPU. The internal machine

cycle is bounded by the rising edges of this signal. This signal goes to the high-impedance state when OFF is active

(low).