Datenblatt-Suchmaschine für elektronische Bauteile |
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UA592 Datenblatt(PDF) 3 Page - Texas Instruments |
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UA592 Datenblatt(HTML) 3 Page - Texas Instruments |
3 / 10 page Absolute Maximum Ratings If MilitaryAerospace specified devices are required please contact the National Semiconductor Sales OfficeDistributors for availability and specifications Storage Temperature Range Ceramic DIP b 65 Cto a175 C Molded DIP SO-8 b 65 Cto a150 C Operating Temperature Range Extended (mA592M) b 55 Cto a125 C Commercial (mA592C) 0 Cto a70 C Lead Temperature Ceramic DIP (Soldering 60 sec) 300 C Molded DIP and SO Package (Soldering 10 sec) 265 C Internal Power Dissipation (Notes 1 2) 8L-Molded DIP 093W SO-8 081W 14L-Molded DIP 104W 14L-Ceramic DIP 136W Supply Voltage g 80V Differential Input Voltage g 50V Common Mode Input Voltage g 60V Output Current 10 mA mA592 and mA592C Electrical Characteristics TA e 25 C VCC e g60V unless otherwise specified Symbol Parameter Conditions mA592 mA592C Units (Notes 3 4) Min Typ Max Min Typ Max AVD Differential Voltage RL e 20 kX Gain 1 300 400 500 250 400 600 VV Gain VO e 30 VP–P Gain 2 90 100 110 80 100 120 BW Bandwidth RS e 50X Gain 1 40 40 MHz Gain 2 90 90 tr Risetime RS e 50X Gain 1 105 105 ns VO e 10 VP–P Gain 2 45 10 45 12 tPD Propagation Delay RS e 50X Gain 1 75 75 ns VO e 10 VP–P Gain 2 60 10 60 10 ZI Input Impedance Gain 1 40 40 kX Gain 2 20 30 10 30 CI Input Capacitance Gain 2 20 20 pF IIO Input Offset Current 04 30 04 50 m A IIB Input Bias Current 90 20 90 30 m A en Input Noise Voltage RS e 50X 12 12 m Vrms BW e 10 kHz to 10 MHz VIR Input Voltage Range g 10 g 10 V CMR Common Mode Rejection VCM e 10V Gain 2 60 86 60 86 dB PSRR Power Supply D VCC e g05V Gain 2 50 70 50 70 dB Rejection Ratio VOO Output Offset Voltage Gain 1 06 15 06 15 V Gain 2 035 075 035 075 VOCM Output Common 24 29 34 24 29 34 V Mode Voltage VOP Output Voltage Swing 30 40 30 40 VP–P IOb Output Sink Current 25 36 25 36 mA RO Output Resistance 20 20 X ICC Supply Current 18 24 18 24 mA Note 1 TJ Max e 150 C for the Molded DIP and SOIC and 175 C for the Ceramic DIP Note 2 Ratings apply to ambient temperature at 25 C Above this temperature derate the 8L-Molded DIP at 75 mW C the SO-8 at 65 mW C the 14L-Molded DIP at 83 mW C and the 14L-Ceramic DIP at 91 mW C Note 3 Gain Select leads G1A and G1B connected together for Gain 1 and Gain Select leads G2A and G2B connected together for Gain 2 Note 4 Gain 2 not applicable to 8 lead device 2 |
Ähnliche Beschreibung - UA592 |
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