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SM320C50PQI80EP Datenblatt(PDF) 11 Page - Texas Instruments |
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SM320C50PQI80EP Datenblatt(HTML) 11 Page - Texas Instruments |
11 / 29 page SM320C50EP DIGITAL SIGNAL PROCESSOR SGUS040A − AUGUST 2002 − REVISED JANUARY 2006 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 CLOCK CHARACTERISTICS AND TIMING The C50 can use either its internal oscillator or an external frequency source for a clock. The clock mode is determined by the CLKMD1 and CLKMD2 pins. Table 3 outlines the selection of the clock mode by these pins. Table 3. Clock Mode Selection CLKMD1 CLKMD2 CLOCK SOURCE 1 0 External divide-by-one clock option 0 1 Reserved for test purposes 1 1 External divide-by-two option or internal divide-by-two clock option with an external crystal 0 0 External divide-by-two option with the internal oscillator disabled internal divide-by-two clock option with external crystal The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN. The frequency of CLKOUT1 is one-half the crystal oscillating frequency. The crystal should be in either fundamental or overtone operation and parallel resonant, with an effective series resistance of 30 Ω and a power dissipation of 1 mW; it should be specified at a load capacitance of 20 pF. Overtone crystals require an additional tuned LC circuit. Figure 4 shows an external crystal (fundamental frequency) connected to the on-chip oscillator. recommended operating conditions for internal divide-by-two clock option MIN NOM MAX UNIT fx Input clock frequency 0 † 66 MHz C1, C2 Load capacitance 10 pF † This device uses a fully static design and, therefore, can operate with tc(CI) approaching ∞. The device is characterized at frequencies approaching 0 Hz but is tested at a minimum of 3.3 MHz to meet device test time requirements. X1 X2 /CLKIN C1 C2 Crystal Figure 4. Internal Clock Option |
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Ähnliche Beschreibung - SM320C50PQI80EP |
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