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SN74ACT16374-EP Datenblatt(PDF) 1 Page - Texas Instruments |
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SN74ACT16374-EP Datenblatt(HTML) 1 Page - Texas Instruments |
1 / 10 page SN74ACT16374Q-EP 16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS SCAS679B – MAY 2002 – REVISED JULY 2002 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Controlled Baseline – One Assembly/Test Site, One Fabrication Site D Extended Temperature Performance of –40 °C to 125°C D Enhanced Diminishing Manufacturing Sources (DMS) Support D Enhanced Product Change Notification D Qualification Pedigree† D Member of the Texas Instruments Widebus Family D Inputs Are TTL-Voltage Compatible D 3-State Bus Driving True Outputs D Flow-Through Architecture Optimizes PCB Layout D Distributed VCC and GND Pins Minimize High-Speed Switching Noise † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, highly accelerated stress test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. description The SN74ACT16374Q-EP is a 16-bit edge-triggered D-type flip-flop with 3-state outputs, designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs. An output-enable (OE) input can be used to place the outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state provides the capability to drive bus lines in a bus-organized system, without need for interface or pullup components. OE does not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. ORDERING INFORMATION TA PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING –40 °C to 125°C SSOP – DL Tape and reel SN74ACT16374QDLREP ACT16374QEP ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE 1CLK 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2CLK DL PACKAGE (TOP VIEW) |
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