Datenblatt-Suchmaschine für elektronische Bauteile |
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CXA3086 Datenblatt(PDF) 5 Page - Sony Corporation |
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CXA3086 Datenblatt(HTML) 5 Page - Sony Corporation |
5 / 30 page – 5 – CXA3086Q 27 CLK/T Clock input. 10 RESETN/T TTL TTL Vcc or GND Reset input. When left open, this input goes to high level. When the input is set to low level, the built-in CLK frequency divider circuit can be reset. 42 INV Data output polarity inversion input. When left open, this input goes to high level. (See Table 1. I/O Correspondence Table.) Power saving input. When the input is set to low level, the power saving mode is set. In this time the all TTL outputs go into the high-impedance state. Normally, set to high level or left open. 41 SELECT Data output mode selection. (See Table 2. Operating Mode Table.) +4.0V (typ.) VRTS +r1 x Iref 22 VRTS Reference voltage sense. By-pass to AGND with a 0.1µF chip capacitor. 21 VRT Top reference voltage. By-pass to AGND with a 1µF tantal capacitor and a 0.1µF chip capacitor. 16 VRB Bottom reference voltage. By-pass to AGND with a 1µF tantal capacitor and a 0.1µF chip capacitor. VRBS –r2 x Iref +2.0V (typ.) 15 VRBS Reference voltage sense. By-pass to AGND with a 0.1µF chip capacitor. DVCC1 DGND1 1.5V r/2 r DVEE3 10 27 DVCC1 DGND1 DVEE3 44 42 DVCC1 DGND1 DVEE3 41 r1 Comparator 63 r r2 r r r Comparator 62 Comparator 2 r r r r Comparator 1 22 21 16 15 I I I 44 PS O I I O Pin No. Symbol I/O Standard voltage level Equivalent circuit Description I |
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