—11—

CXA3235/3236N

Description of PLL Block

1) Mode Setting Method

The modes for each frequency step are set according to the MS pin voltage.

Symbol

ADSW

SCL

SDA

Description

Address selection

SCL input

SDA I/O

Mode

B-0

B-1

B-2

B-3

B-4

MS pin voltage

OPEN

Main

divider

15 bit

14 bit

15 bit

15 bit

15 bit

Reference

divider

1024

512

640

512

512/

640/

1024

Reference frequency

3.90625 kHz

7.8125 kHz

6.25 kHz

7.8125 kHz

7.8125 kHz/

6.25 kHz/

3.90625 kHz

Frequency

step∗

31.25 kHz

62.5 kHz

50 kHz

62.5 kHz

62.5 kHz/

50 kHz/

31.25 kHz

∗ Frequency step is for when X’tal OSC = 4 MHz.

2) Address Setting

The responding address can be changed according to the ADSW pin voltage, so that multiple PLL can

exist within one system.

Address

ADSW pin voltage

MA1

0

0

1

1

MA0

0

1

0

1