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LB11696V-D Datenblatt(PDF) 7 Page - Sanyo Semicon Device |
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LB11696V-D Datenblatt(HTML) 7 Page - Sanyo Semicon Device |
7 / 16 page No.8087-7/16 LB11696V Pin No. Pin Name Pin Description Equivalent circuit 23 PWM IN PWM pulse input A low-level input specifies the output drive state, and a high-level or open input specifies the output off state. When this pin is used for control, the TOC pin voltage must be set to a control amplifier input that results in a 100% duty. VREG 50 k Ω 3.5 k Ω 23 24 F/R Forward/reverse input VREG 50 k Ω 3.5 k Ω 24 25 HP Hall signal output (This is an open-collector output) One of four output types is selected by the N1 and N2 pin settings. VREG 25 Continued from preceding page. Continued on next page. 22 S/S Start/Stop input A low-level input sets the IC to start mode, and a high- level input sets it to stop mode. VREG 3.5 k Ω 22 21 CSD Constraint protection circuit operating time setting Insert a capacitor between this pin and ground. This pin must be connected to ground if the constraint protection circuit is not used. VREG 300 Ω 21 |
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Ähnliche Beschreibung - LB11696V-D |
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