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AD1859 Datenblatt(PDF) 8 Page - Analog Devices |
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AD1859 Datenblatt(HTML) 8 Page - Analog Devices |
8 / 16 page REV. A –8– AD1859 Option for Analog De-emphasis Processing The AD1859 includes three pins for implementing an external analog 50/15 µs (or possibly the CCITT J. 17) de-emphasis fre- quency response characteristic. A control pin DEEMP (Pin 2) enables de-emphasis when it is asserted HI. Two analog out- puts, EMPL (Pin 3) and EMPR (Pin 26) are used to switch the required analog components into the output stage of the AD1859. An analog implementation of de-emphasis is superior to a digital implementation in several ways. It is generally lower noise, since digital de-emphasis is usually created using recursive IIR filters, which inject limit cycle noise. Also the digital de-emphasis is be- ing applied in front of the primary analog noise generation source, the DAC modulator, and its high frequency noise contributions are not attenuated. An analog de-emphasis circuit is down- stream from the relatively “noisy” DAC modulator and thus pro- vides a more effective noise reduction role (which was the original intent of the emphasis/de-emphasis scheme). A final key advan- tage of analog de-emphasis is that it is sample rate invariant, so that users can fully exploit the sample rate range of the AD1859 and simultaneously use de-emphasis. Digital implementations gen- erally only support fixed, standard sample rates. Digital Phase Locked Loop The digital PLL is adaptive, and locks to the applied sample rate (on the LRCLK Pin 13) in 100 ms to 200 ms. The digital PLL is initially in “fast” mode, with a wide lock capture bandwidth. The phase detector automatically switches the loop filter into “slow” mode as phase lock is gradually obtained. The loop bandwidth is 15 Hz in slow mode. Since the loop filter is first order, the digital PLL will reject jitter on the left/right clock above 15 Hz, with an attenuation of 6 dB per octave. The jitter rejection frequency response is shown in Figure 1. –60 –42 –54 15 –48 0 –24 –36 –30 –18 –12 –6 0 15360 7680 3840 1920 960 480 240 120 60 30 Hz ABOVE OR BELOW THE SAMPLE FREQUENCY Figure 1. Digital PLL Jitter Rejection OPERATING FEATURES Serial Data Input Port The AD1859 uses the frequency of the left/right input clock to determine the input sample rate. LRCLK must run continu- ously and transition twice per stereo sample period (except in the left-justified DSP serial port style mode, when it transitions four times per stereo sample period). The bit clock (BCLK) is edge sensitive and may be used in a gated or burst mode (i.e., a stream of pulses during data transmission followed by periods of inactivity). The bit clock is only used to write the audio data into the serial input port. It is important that the left/right clock is “clean” with monotonic rising and falling edge transitions and no excessive overshoot or undershoot which could cause false clock triggering of the AD1859. The AD1859’s flexible serial data input port accepts data in twos-complement, MSB-first format. The left channel data field always precedes the right channel data field. The input data consists of either 16 or 18 bits, as established by the 18/16 input control (Pin 8). All digital inputs are specified to TTL logic levels. The input data port is configured by control pins. Serial Input Port Modes The AD1859 uses two multiplexed input pins to control the mode configuration of the input data port. IDPM0 and IDPM1 program the input data port mode as follows: IDPM1 IDPM0 Serial Input Port Mode LO LO Right-Justified (See Figure 2) LO HI I 2S-Justified (See Figure 3) HI LO Left-Justified (See Figure 4) HI HI Left-Justified DSP Serial Port Style (See Figure 5) Figure 2 shows the right-justified mode. LRCLK is HI for the left channel, and LO for the right channel. Data is valid on the rising edge of BCLK. The MSB is delayed 14-bit clock periods (in 18-bit input mode) or 16-bit clock periods (in 16-bit input mode) from an LRCLK transition, so that when there are 64 BCLK periods per LRCLK period, the LSB of the data will be right-justified to the next LRCLK transition. MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB-1 MSB-2 LSB LSB+2 LSB+1 LSB LEFT CHANNEL RIGHT CHANNEL MSB BCLK INPUT SDATA INPUT LRCLK INPUT Figure 2. Right-Justified Mode |
Ähnliche Teilenummer - AD1859 |
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Ähnliche Beschreibung - AD1859 |
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