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AD5311BRM Datenblatt(PDF) 9 Page - Analog Devices |
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AD5311BRM Datenblatt(HTML) 9 Page - Analog Devices |
9 / 15 page REV. 0 AD5301/AD5311/AD5321 –9– 1ns/DIV 2.440 2.455 2.445 2.450 Figure 20. Digital Feedthrough GENERAL DESCRIPTION The AD5301/AD5311/AD5321 are single resistor-string DACs fabricated on a CMOS process with resolutions of 8, 10 and 12 bits respectively. Data is written via a 2-wire serial interface. They operate from single supplies of +2.5 V to +5.5 V and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 V/ µs. The power-supply (V DD) acts as the refer- ence to the DAC. The devices have three programmable power- down modes, in which the DAC may be turned off completely with a high-impedance output, or the output may be pulled low by an on-chip resistor. See Power-Down section. DIGITAL-TO-ANALOG SECTION The architecture of the DAC channel consists of a resistor- string DAC followed by an output buffer amplifier. The voltage at the VDD pin provides the reference voltage for the DAC. Figure 21 shows a block diagram of the DAC architecture. Since the input coding to the DAC is straight binary, the ideal output voltage is given by: V VD OUT DD N = × 2 where: N = DAC resolution D = decimal equivalent of the binary code which is loaded to the DAC register: 0–255 for AD5301 (8 Bits) 0–1023 for AD5311 (10 Bits) 0–4095 for AD5321 (12 Bits) RESISTOR STRING OUTPUT BUFFER AMPLIFIER DAC REGISTER REF(+) VOUT VDD REF(–) Figure 21. DAC Channel Architecture RESISTOR STRING The resistor string section is shown in Figure 22. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at what node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic over all codes. R R R R R TO OUTPUT AMPLIFIER Figure 22. Resistor String OUTPUT AMPLIFIER The output buffer amplifier is capable of generating output voltages to within 1 mV from either rail, which gives an output range of 0.001 V to VDD – 0.001 V. It is capable of driving a load of 2 k Ω to GND and V DD, in parallel with 500 pF to GND. The source and sink capabilities of the output amplifier can be seen in Figure 11. The slew rate is 0.7 V/ µs with a half-scale settling time to ±0.5 LSB (at 8 bits) of 6 µs with the output unloaded. POWER-ON RESET The AD5301/AD5311/AD5321 are provided with a power-on reset function, ensuring that they power up in a defined state. The DAC register is filled with zeros and remains so until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC output while the device is powering up. |
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