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AD5582YRU-REEL7 Datenblatt(PDF) 1 Page - Analog Devices

Teilenummer AD5582YRU-REEL7
Bauteilbeschribung  QUAD, Parallel-Input, Voltage Output, 12-/10-Bit Digital-to-Analog Converter
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Hersteller  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5582YRU-REEL7 Datenblatt(HTML) 1 Page - Analog Devices

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PRELIMINARY TECHNICAL DATA
a
QUAD, Parallel-Input, Voltage Output,
12-/10-Bit Digital-to-Analog Converter
AD5582/AD5583
REV PrC, 23 APR '01
Information furnished by Analog Devices is believed to be accurate and reliable. However,
no responsibility is assumed by Analog Devices for its use; nor for any infringements of
patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106,
Norwood, MA 02062-9106 U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax:781/326-8703
©Analog Devices, Inc., 2000
FEATURES
12-Bit Linearity and Monotonic –40
oC to +125oC
Single +5V to +12V or dual ±5V supply
Unipolar or Bipolar Operation
Double Buffered Registers Enable Simultaneous Multi-
Channels Update
4 Separate Rail-to Rail Reference Inputs
Parallel Interface
Data Readback Capability
5
µs Settling Time
APPLICATIONS
Process Control Equipment
Closed Loop Servo Control
Data Acquisition Systems
Digitally Controlled Calibration
Motor Control
Optical Network Control Loops
GENERAL DESCRIPTION
The AD5582/AD5583 family of quad, 12-/10-bit, voltage-output
digital-to-analog converter is designed to operate from a single +5
to +15 volt or a dual ±5V supply. Built using a CBCMOS process,
this monolithic DAC offers the user low cost, and ease-of-use in
single or dual-supply systems.
The applied external reference VREF determines the full-scale
output voltage. Valid VREF values include VSS<VREF<VDD resulting
in a wide selection of full scale outputs. For multiplying
applications AC inputs can be as large as |VDD-VSS|. Two on-board
precision trimmed resistors are available for 4-Quadrant
configurations.
A doubled-buffered parallel interface offers 25Mbps data load rates.
A common level-sensitive load-DAC strobe (
LDAC) input allows
simultaneous update of all DAC outputs from previously loaded
Input Registers. An external asynchronous reset (
RS) forces all
registers to the zero code state when MSB='0' or to midscale when
MSB='1'.
Both parts are offered in the same pin-out to allow users to select
the amount of resolution appropriate for their application without
circuit card redesign.
The AD5582/AD5583 are specified over the extended industrial
(-40°C to +125°C) temperature range. Packages available include
thin 1.1 mm TSSOP-48 package.
FUNCTIONAL DIAGRAM
11
23
13
12
6
7
V
OB
9
V
OC
3
4
5
20
V
OA
2
1
10
14
15
V
RLA
V
RHA
V
RLB
V
RHB
V
RHD
V
RLD
V
RHC
V
RLC
V
SS
V
DD
AGND
V
OD
IN
REG
I
N
T
E
R
F
A
C
E
OE
CONTROL
LOGIC
ADDR
DECODE
DAC
REG
27
24
25
26
31
28
29
30
35
32
33
34
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
CS
W/R
LDAC
DGND
VLOGIC
MSB
22
A1
A0
AD5582
36
37
21
17
19
16
Do
Di
18
RS
DVDD
RA
38
RB
RC
20k
20k
39
40
8
DA C A
DA C B
DA C C
DA C D
A D R 421
V
RE F L
A
B
C
D
V
RE F H
A
B
C
D
R
A
R
B
R
C
A D 5582
DIG IT A L CIRCUIT R Y O M IT T E D F O R CL A R IT Y
+2.5 V
-2 .5 V
±2 .5 V
±2 .5 V
±2 .5 V
±2 .5 V
Figure 1 Using Onboard Offset resistors to generate a negative
voltage REF


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