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AD5325BRM-REEL Datenblatt(PDF) 10 Page - Analog Devices |
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AD5325BRM-REEL Datenblatt(HTML) 10 Page - Analog Devices |
10 / 20 page REV. F –10– AD5305/AD5315/AD5325 FUNCTIONAL DESCRIPTION The AD5305/AD5315/AD5325 are quad resistor-string DACs fabricated on a CMOS process with resolutions of 8, 10, and 12 bits, respectively. Each contains four output buffer amplifiers and is written to via a 2-wire serial interface. They operate from single supplies of 2.5 V to 5.5 V, and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 V/ µs. The four DACs share a single reference input pin. The devices have three programmable power-down modes, in which all DACs may be turned off completely with a high impedance output, or the outputs may be pulled low by on-chip resistors. Digital-to-Analog Section The architecture of one DAC channel consists of a resistor-string DAC followed by an output buffer amplifier. The voltage at the REFIN pin provides the reference voltage for the DAC. Figure 4 shows a block diagram of the DAC architecture. Since the input coding to the DAC is straight binary, the ideal output voltage is given by V VD OUT REF N = × 2 IDD ( A) 300 350 600 400 450 500 550 VDD = 5V VDD = 3V TPC 19. IDD Histogram with VDD = 3 V and VDD = 5 V VDD = 5V TA = 25 C VREF (V) 0.02 –0.02 01 3 0.01 –0.01 46 0 25 TPC 22. Full-Scale Error vs. VREF 1 s/DIV 2.48 2.49 2.47 2.50 TPC 20. AD5325 Major-Code Transition Glitch Energy 50ns/DIV TPC 23. DAC-to-DAC Crosstalk FREQUENCY (Hz) 10 –40 10 –20 –30 0 –10 100 1k 10k 100k 1M 10M –50 –60 TPC 21. Multiplying Bandwidth (Small-Signal Frequency Response) where D = decimal equivalent of the binary code, which is loaded to the DAC register: 0–255 for AD5305 (8 bits) 0–1023 for AD5315 (10 bits) 0–4095 for AD5325 (12 bits) N = DAC resolution INPUT REGISTER REFIN OUTPUT BUFFER AMPLIFIER VOUTA RESISTOR STRING DAC REGISTER Figure 4. DAC Channel Architecture |
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