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AD8023AR-REEL Datenblatt(PDF) 10 Page - Analog Devices |
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AD8023AR-REEL Datenblatt(HTML) 10 Page - Analog Devices |
10 / 11 page AD8023 REV. A –10– Figure 33. 50% Overload Recovery, Gain = +10, (RF = 300 Ω, RL = 1 kΩ, VS = ±7.5 V) As noted in the warning under Maximum Power Dissipation, a high level of input overdrive in a high noninverting gain circuit can result in a large current flow in the input stage. Though this current is internally limited to about 30 mA, its effect on the total power dissipation may be significant. Disable Mode Operation Pulling the voltage on any one of the Disable pins about 1.6 V up from the negative supply will put the corresponding amplifier into a disabled, powered down, state. In this condition, the amplifier’s quiescent current drops to about 1.3 mA, its output becomes a high impedance, and there is a high level of isolation from input to output. In the case of a gain of two line driver for example, the impedance at the output node will be about the same as for a 1.5 k Ω resistor (the feedback plus gain resistors) in parallel with a 12 pF capacitor. Leaving the Disable pin disconnected (floating) will leave the corresponding amplifier operational, in the enabled state. The input impedance of the disable pin is about 25 k Ω in parallel with a few picofarads. When driven to 0 V, with the negative supply at –7.5 V, about 100 µA flows into the disable pin. When the disable pins are driven by complementary output CMOS logic, on a single 5 V supply, the disable and enable times are about 50 ns. When operated on dual supplies, level shifting will be required from standard logic outputs to the Disable pins. Figure 33 shows one possible method, which results in a negligible increase in switching time. +7.5V 10k TO DISABLE PIN VI VI HIGH => AMPLIFIER ENABLED VI LOW => AMPLIFIER DISABLED –7.5V 4k 15k +5 Figure 34. Level Shifting to Drive Disable Pins on Dual Supplies The AD8023’s input stages include protection from the large differential input voltages that may be applied when disabled. Internal clamps limit this voltage to about ±3 V. The high input to output isolation will be maintained for voltages below this limit. Figure 31. Circuit for Driving a Capacitive Load Table II. Recommended Feedback and Series Resistors vs. Capacitive Load and Gain RS – Ohms CL – pF RF – Ohms G = 2 G ≥ 3 20 2k 0 0 50 2k 10 10 100 2k 15 15 200 3k 10 10 300 3k 10 10 ≥500 3k 10 10 Figure 32. Pulse Response Driving a Large Load Capacitor. CL = 300 pF, G = +3, RF = 750 Ω, RS = 16.9 Ω, RL = 10 kΩ Overload Recovery The three important overload conditions are: input common- mode voltage overdrive, output voltage overdrive, and input current overdrive. When configured for a low closed-loop gain, this amplifier will quickly recover from an input common-mode voltage overdrive; typically in under 25 ns. When configured for a higher gain, and overloaded at the output, the recovery time will also be short. For example, in a gain of +10, with 50% overdrive, the recovery time of the AD8023 is about 20 ns (see Figure 31). For higher overdrive, the response is somewhat slower. For 100% overdrive, (in a gain of +10), the recovery time is about 80 ns. V IN V O V IN V O 4 +VS AD8023 1.0 F 0.1 F 11 1.0 F 0.1 F –VS RG RT VIN 15 CL VO RF RS |
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Ähnliche Beschreibung - AD8023AR-REEL |
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