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AD876JST-REEL Datenblatt(PDF) 10 Page - Analog Devices |
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AD876JST-REEL Datenblatt(HTML) 10 Page - Analog Devices |
10 / 16 page REV. B –10– AD876 AD876 +5V 8 6 5 7 1/2 AD826 2 3 6 1/2 AD826 4 REFT REFB REFTS REFTF REFBS REFBF C3 0.1 F C4 0.1 F C2 0.1 F C5 0.1 F C1 0.1 F Figure 19. Kelvin Connected Reference Using the AD826 By connecting the op amp feedback through the sense connec- tions of the AD876, the outputs of the op amps automatically adjust to compensate for the voltage drops that occur within the converter. The AD826 has the advantage of being able to maintain stability while driving unlimited capacitive loads. As a result, 0.1 µF capacitors C1, C2, and C3 can connect directly to the outputs of the op amps. These decoupling capacitors reduce high frequency transients. Capacitors C4 and C5 shunt across the internal resistors of the force sense connections and prevent instability. This configuration provides excellent performance and a mini- mal number of components. The circuit also offers the advan- tage of operating from a single +5 V supply. While alternative op amps may also be suitable, consider the stability of these op amps while driving capacitive loads. The circuit shown in Figure 20 allows a wider selection of op amps when compared with the previous configuration. An AD876 1/2 OP-295 10 F 0.1 F REFT REFTS REFTF 47nF 20k 10 1/2 OP-295 10 F 0.1 F REFB REFBS REFBF 47nF 20k 10 22 F Figure 20. Kelvin Connected Reference Using the OP295 OP295 dual, single-supply op amp provides stable 3.6 V and 1.6 V reference voltages. The AD822 dual op amp is also suit- able for single-supply applications. Each half of the OP295 is compensated to drive the 10 µF and 0.1 µF decoupling capaci- tors at the REFTF and REFBF pins and maintain stability. Like any high resolution converter, the layout and decoupling of the reference is critical. The actual voltage digitized by the AD876 is relative to the reference voltages. In Figure 21, for example, the reference return and the bypass capacitors are connected to the shield of the incoming analog signal. Distur- bances in the ground of the analog input, that will be common- mode to the REFT, REFB, and AIN pins because of the common ground, are effectively removed by the AD876’s high common-mode rejection. High frequency noise sources, VN1 and VN2, are shunted to ground by decoupling capacitors. Any voltage drops between the analog input ground and the reference bypassing points will be treated as input signals by the converter via the reference inputs. Consequently, the reference decoupling capacitors should be connected to the same analog ground point used to define the analog input voltage. (For further suggestions, see the “Grounding and Layout Rules” section of the data sheet.) 4V VN1 2V VN2 REFTF REFBF AIN AD876 Figure 21. Recommended Bypassing for the Reference Inputs CLOCK INPUT The AD876 clock input is buffered internally with an inverter powered from the DRVDD pin. This feature allows the AD876 to accommodate either +5 V or +3.3 V CMOS logic input sig- nal swings with the input threshold for the CLK pin nominally at DRVDD/2. The AD876’s pipelined architecture operates on both rising and falling edges of the input clock. To minimize duty cycle varia- tions the recommended logic family to drive the clock input is high speed or advanced CMOS (HC/HCT, AC/ACT) logic. CMOS logic provides both symmetrical voltage threshold levels and sufficient rise and fall times to support 20 MSPS operation. The AD876 is designed to support a conversion rate of 20 MSPS; running the part at slightly faster clock rates may be possible, although at reduced performance levels. Conversely, some slight performance improvements might be realized by clocking the AD876 at slower clock rates. The power dissipated by the correction logic and output buffers is largely proportional to the clock frequency; running at reduced clock rates provides a reduction in power consumption. Figure 8 illustrates this trade-off. DIGITAL INPUTS AND OUTPUTS Each of the AD876 digital control inputs, THREE-STATE and STBY, has an input buffer powered from the DRVDD supply pins. With DRVDD set to +5 V, all digital inputs readily inter- face with +5 V CMOS logic. For interfacing with lower voltage CMOS logic, DRVDD can be set to 3.3 V, effectively lowering the nominal input threshold of all digital inputs to 3.3 V/2 = 1.65 V. The format of the digital output is straight binary. Table I shows the output format for the case where REFTS = 4 V and REFBS = 2 V. |
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