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ADM1025 Datenblatt(PDF) 2 Page - Analog Devices

Teilenummer ADM1025
Bauteilbeschribung  Low-Cost PC Hardware Monitor ASIC
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Direct Link  http://www.analog.com
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REV. A
–2–
ADM1025/ADM1025A–SPECIFICATIONS (T
A = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER SUPPLY
Supply Voltage, VCC
3.0
3.30
5.5
V
(Note 1)
Supply Current, ICC
1.4
2.5
mA
Interface Inactive, ADC Active
32
500
µA
Standby Mode (Note 2)
TEMPERATURE-TO-DIGITAL CONVERTER
Internal Sensor Accuracy
±3
°C
Resolution
1
°C
External Diode Sensor Accuracy
±5
°C
±3
°C60°C ≤ T
A
≤ 100°C; V
CC = 3.3 V
Resolution
1
°C
Remote Sensor Source Current
180
µA
High Level
11
µA
Low Level
ANALOG-TO-DIGITAL CONVERTER
(INCLUDING MUX AND ATTENUATORS)
Total Unadjusted Error, TUE
±2
%
(Note 3)
Differential Nonlinearity, DNL
±1
LSB
Power Supply Sensitivity
±1
%/V
Conversion Time (Analog Input or Internal Temperature)
11.6
ms
(Note 4)
Conversion Time (External Temperature)
34.8
ms
(Note 4)
Input Resistance (2.5 V, 3.3 V, 5 V, 12 V, VCCPIN)
100
140
250
k
OPEN-DRAIN DIGITAL OUTPUT ADD/
RST/INT/NTO
Output Low Voltage, VOL
0.4
V
IOUT = –6.0 mA; VCC = 3 V
High Level Output Leakage Current, IOH
0.1
1
µAV
OUT = VCC; VCC = 3 V
RST Pulsewidth
20
45
ms
OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)
Output Low Voltage, VOL
0.4
V
IOUT = –6.0 mA; VCC = 3 V
High Level Output Leakage Current, IOH
0.1
1
µAV
OUT = VCC
SERIAL BUS DIGITAL INPUTS (SCL, SDA)
Input High Voltage, VIH
2.1
V
Input Low Voltage, VIL
0.8
V
Hysteresis
500
mV
DIGITAL INPUT LOGIC LEVELS
(ADD, VID0–VID4, NTI)
5
VID0–3 Input Resistance
100
k
ADM1025 Only
VID4 Input Resistance
300
k
ADM1025 Only
100
k
ADM1025A
Input High Voltage, VIH
6
2.1
V
Input Low Voltage, VIL
6
0.8
V
DIGITAL INPUT LEAKAGE CURRENT
Input High Current, IIH
–1
µAV
IN = VCC
Input Low Current, IIL
1
µAV
IN = 0
Input Capacitance, CIN
5pF
SERIAL BUS TIMING
Clock Frequency, fSCLK
400
kHz
See Figure 1
Glitch Immunity, tSW
50
ns
See Figure 1
Bus Free Time, tBUF
1.3
µs
See Figure 1
Start Setup Time, tSU:STA
600
ns
See Figure 1
Start Hold Time, tHD:STA
600
ns
See Figure 1
Stop Condition Setup Time tSU:STO
600
ns
See Figure 1
SCL Low Time, tLOW
1.3
µs
See Figure 1
SCL High Time, tHIGH
0.6
µs
See Figure 1
SCL, SDA Rise Time, tR
300
ns
See Figure 1
SCL, SDA Fall Time, tF
300
ns
See Figure 1
Data Setup Time, tSU:DAT
100
ns
See Figure 1
Data Hold Time, tHD:DAT
300
ns
See Figure 1
NOTES
1All voltages are measured with respect to GND, unless otherwise specified.
2Typicals are at T
A = 25
°C and represent most likely parametric norm. Shutdown current typ is measured with V
CC = 3.3 V.
3TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC, multiplexer and on-chip input attenuators, including an external series input
protection resistor value between zero and 1 k
Ω.
4Total monitoring cycle time is nominally 114.4 ms. Monitoring Cycle consists of 6 Voltage + 1 Internal Temperature + 1 External Temperature readings.
5ADD is a three-state input that may be pulled high, low or left open-circuit.
6Timing specifications are tested at logic levels of V
IL = 0.8 V for a falling edge and VIH = 2.2 V for a rising edge.
Specifications subject to change without notice.


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