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DAC08HQ Datenblatt(PDF) 10 Page - Analog Devices |
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DAC08HQ Datenblatt(HTML) 10 Page - Analog Devices |
10 / 12 page DAC08 –10– REV. A REFERENCE AMPLIFIER COMPENSATION FOR MULTIPLYING APPLICATIONS AC reference applications will require the reference amplifier to be compensated using a capacitor from pin 16 to V–. The value of this capacitor depends on the impedance presented to pin 14: for R14 values of 1.0, 2.5 and 5.0 k Ω, minimum values of C C are 15, 37, and 75 pF. Larger values of R14 require proportion- ately increased values of CC for proper phase margin, such that the ratio of CC (pF) to R14 (k Ω) = 15. For fastest response to a pulse, low values of R14 enabling small CC values should be used. If pin 14 is driven by a high imped- ance such as a transistor current source, none of the above val- ues will suffice and the amplifier must be heavily compensated which will decrease overall bandwidth and slew rate. For R14 = 1 k Ω and C C = 15 pF, the reference amplifier slews at 4 mA/ µs enabling a transition from IREF = 0 to IREF = 2 mA in 500 ns. Operation with pulse inputs to the reference amplifier may be accommodated by an alternate compensation scheme. This technique provides lowest full-scale transition times. An internal clamp allows quick recovery of the reference amplifier from a cutoff (IREF = 0) condition. Full-scale transition (0 mA to 2 mA) occurs in 120 ns when the equivalent impedance at pin 14 is 200 Ω and C C = 0. This yields a reference slew rate of 16 mA/ µs which is relatively independent of RIN and VIN values. LOGIC INPUTS The DAC08 design incorporates a unique logic input circuit which enables direct interface to all popular logic families and provides maximum noise immunity. This feature is made pos- sible by the large input swing capability, 2 µA logic input cur- rent and completely adjustable logic threshold voltage. For V– = –15 V, the logic inputs may swing between –10 V and +18 V. This enables direct interface with +15 V CMOS logic, even when the DAC08 is powered from a +5 V supply. Minimum in- put logic swing and minimum logic threshold voltage are given by: V– plus ( IREF × 1 kΩ) plus 2.5 V. The logic threshold may be adjusted over a wide range by placing an appropriate voltage at the logic threshold control pin (pin 1, VLC). The appropriate graph shows the relationship between VLC and VTH over the temperature range, with VTH nominally 1.4 above VLC. For TTL and DTL interface, simply ground pin 1. When interfacing ECL, an IREF = 1 mA is recommended. For interfacing other logic families, see preceding page. For general set-up of the logic control circuit, it should be noted that pin 1 will source 100 µA typical; external circuitry should be designed to accommodate this current. Fastest settling times are obtained when pin 1 sees a low imped- ance. If pin 1 is connected to a 1 k Ω divider, for example, it should be bypassed to ground by a 0.01 µF capacitor. ANALOG OUTPUT CURRENTS Both true and complemented output sink currents are provided where IO + I O = IFS. Current appears at the “true” (IO) output when a “1” (logic high) is applied to each logic input. As the bi- nary count increases, the sink current at pin 4 increases propor- tionally, in the fashion of a “positive logic” D/A converter. When a “0” is applied to any input bit, that current is turned off at pin 4 and turned on at pin 2. A decreasing logic count increases I O as in a negative or inverted logic D/A converter. Both outputs may be used simultaneously. If one of the outputs is not required it must be connected to ground or to a point capable of sourcing IFS; do not leave an unused output pin open. Both outputs have an extremely wide voltage compliance en- abling fast direct current-to-voltage conversion through a resis- tor tied to ground or other voltage source. Positive compliance is 36 V above V– and is independent of the positive supply. Negative compliance is given by V– plus (IREF × 1 kΩ) plus 2.5 V. The dual outputs enable double the usual peak-to-peak load swing when driving loads in quasi-differential fashion. This fea- ture is especially useful in cable driving, CRT deflection and in other balanced applications such as driving center-tapped coils and transformers. POWER SUPPLIES The DAC08 operates over a wide range of power supply volt- ages from a total supply of 9 V to 36 V. When operating at sup- plies of ±5 V or less, I REF ≤ 1 mA is recommended. Low reference current operation decreases power consumption and increases negative compliance, reference amplifier negative common-mode range, negative logic input range, and negative logic threshold range; consult the various figures for guidance. For example, operation at –4.5 V with IREF = 2 mA is not rec- ommended because negative output compliance would be re- duced to near zero. Operation from lower supplies is possible, however at least 8 V total must be applied to insure turn-on of the internal bias network. Symmetrical supplies are not required, as the DAC08 is quite insensitive to variations in supply voltage. Battery operation is feasible as no ground connection is required: however, an artifi- cial ground may be used to insure logic swings, etc. remain be- tween acceptable limits. Power consumption may be calculated as follows: Pd = (I+) (V+) + (I–) (V–). A useful feature of the DAC08 design is that supply current is constant and independent of input logic states; this is useful in cryptographic applications and further serves to reduce the size of the power supply bypass capacitors. TEMPERATURE PERFORMANCE The nonlinearity and monotonicity specifications of the DAC08 are guaranteed to apply over the entire rated operating tempera- ture range. Full-scale output current drift is low, typically ±10 ppm/°C, with zero-scale output current and drift essentially negligible compared to 1/2 LSB. The temperature coefficient of the reference resistor R14 should match and track that of the output resistor for minimum overall full-scale drift. Settling times of the DAC08 decrease approxi- mately 10% at –55 °C; at +125°C an increase of about 15% is typical. The reference amplifier must be compensated by using a capaci- tor from pin 16 to V–. For fixed reference operation, a 0.01 µF capacitor is recommended. For variable reference applications, see previous section entitled “Reference Amplifier Compensa- tion for Multiplying Applications”. |
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