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AD5263BRUZ20-REEL7 Datenblatt(PDF) 4 Page - Analog Devices |
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AD5263BRUZ20-REEL7 Datenblatt(HTML) 4 Page - Analog Devices |
4 / 28 page AD5263 Data Sheet Rev. F | Page 4 of 28 Parameter Symbol Conditions Min Typ1 Max Unit POWER SUPPLIES Logic Supply8 V L 2.7 5.5 V Power Single-Supply Range V DD RANGE V SS = 0 V 4.5 16.5 V Power Dual-Supply Range V DD/SS RANGE ±4.5 ±7.5 V Logic Supply Current9 I L V L = +5 V 25 60 µA Positive Supply Current I DD V IH = +5 V or VIL = 0 V 1 µA Negative Supply Current I SS V SS = –5 V 1 µA Power Dissipation10 P DISS V IH = +5 V or VIL = 0 V, VDD = +5 V, V SS = –5 V 0.6 mW Power Supply Sensitivity PSS ∆V DD = +5 V ± 10% 0.002 0.01 %/% DYNAMIC CHARACTERISTICS6, 11 Bandwidth (3 dB) BW R AB = 20 kΩ/50 kΩ/200 kΩ 300/150/35 kHz Total Harmonic Distortion THD W V A = 1 V rms, VB = 0 V, f = 1 kHz, R AB = 20 kΩ 0.05 % V W Settling Time 12 t S V A = 10 V, VB = 0 V, ±1 LSB error band 2 µs Resistor Noise Voltage e N_WB R WB = 10 kΩ, f = 1 kHz, RS = 0 9 nV/√Hz 1 Typicals represent average readings at +25°C and V DD = +5 V, VSS = −5 V. 2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD = +5 V and VSS = –5 V. 3 V AB = VDD, Wiper (VW) = no connect. 4 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 The A, B, and W resistor terminals have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode. 8 V L is limited to VDD or 5.5 V, whichever is less. 9 Worst-case supply current consumed when all logic-input levels set at 2.4 V, standard characteristic of CMOS logic. 10 P DISS is calculated from IDD × VDD. CMOS logic level inputs result in minimum power dissipation. 11 All dynamic characteristics use V DD = +5 V, VSS = −5 V, VL = +5 V. 12 Settling time depends on value of V DD, RL, and CL. |
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Ähnliche Beschreibung - AD5263BRUZ20-REEL7 |
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