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74ACTQ16540MTD Datenblatt(PDF) 4 Page - Fairchild Semiconductor

Teilenummer 74ACTQ16540MTD
Bauteilbeschribung  16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs
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Hersteller  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

74ACTQ16540MTD Datenblatt(HTML) 4 Page - Fairchild Semiconductor

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AC Electrical Characteristics
Note 8: Voltage Range 5.0 is 5.0V
± 0.5V.
Extended AC Electrical Characteristics
Note 9: Voltage Range 5.0 is 5.0V
± 0.5V.
Note 10: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.).
Note 11: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 12: 3-STATE delays are load dominated and have been excluded from the datasheet.
Note 13: The Output Disable Time is dominated by the RC network (500
Ω, 250 pF) on the output and has been excluded from the datasheet.
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-
to-LOW (tOST).
Capacitance
VCC
TA = +25°CTA = −40°C to +85°C
Symbol
Parameter
(V)
CL = 50 pF
CL = 50 pF
Units
(Note 8)
Typ
Min
Max
Min
Max
tPLH
Propagation Delay
5.0
2.7
4.9
7.3
2.7
7.8
ns
tPHL
Data to Output
3.0
5.1
7.3
3.0
7.8
tPZH
Output Enable
5.0
2.5
4.8
7.4
2.5
7.9
ns
tPZL
Time
2.7
5.3
8.0
2.7
8.5
tPHZ
Output Disable
5.0
2.5
5.4
8.3
2.5
8.7
ns
tPLZ
Time
2.3
5.0
7.4
2.3
7.9
TA = −40°C to +85°C
CL = 50 pF
TA = −40°C to +85°C
Symbol
Parameter
VCC
16 Outputs Switching
CL = 250 pF
Units
(V)
(Note 10)
(Note 11)
(Note 9)
Min
Typ
Max
Min
Max
tPLH
Propagation Delay,
5.0
4.0
12.6
5.6
15.5
ns
tPHL
Data to Output
4.0
10.0
5.6
13.6
tPZH
Output Enable Time
5.0
3.2
10.8
(Note 12)
ns
tPZL
3.4
10.8
tPHZ
Output Disable Time
5.0
3.8
9.5
(Note 13)
ns
tPLZ
3.1
9.2
tOSHL
Pin to Pin Skew,
5.0
1.2
ns
(Note 14)
HL Data to Output
tOSLH
Pin to Pin Skew,
5.0
2.5
ns
(Note 14)
LH Data to Output
tOST
Pin to Pin Skew,
5.0
4.3
ns
(Note 14)
LH/HL Data to Output
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Pin Capacitance
4.5
pF
VCC = 5.0V
CPD
Power Dissipation Capacitance
30
pF
VCC = 5.0V


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