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2

Unit Loading/Fan Out

Truth Table

H (h)

= HIGH Voltage Level

L (h)

= LOW Voltage Level

X

= Immaterial

 = HIGH-to-LOW Clock Transition

Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.

Logic Diagram

(one half shown)

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Pin Names

Description

U.L.

HIGH/LOW

Data Inputs

1.0/1.0

20

µA/−0.6 mA

CP

Clock Pulse Input (Active Falling Edge)

1.0/8.0

20

µA/−4.8 mA

Direct Clear Input (Active LOW)

1.0/10.0

20

µA/−6.0 mA

Direct Set Inputs (Active LOW)

1.0/5.0

20

µA/−3.0 mA

Outputs

50/33.3

−1 mA/20 mA

Inputs

Outputs

CP

JK

Q

Q

L

H

XXX

H

L

H

L

XXX

L

H

L

L

XXX

H

H

HH



hh

HH



lh

L

H

HH



hl

H

L

HH



ll