Datenblatt-Suchmaschine für elektronische Bauteile |
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74VCX16373MTD Datenblatt(PDF) 1 Page - Fairchild Semiconductor |
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74VCX16373MTD Datenblatt(HTML) 1 Page - Fairchild Semiconductor |
1 / 10 page © 2005 Fairchild Semiconductor Corporation DS500065 www.fairchildsemi.com October 1997 Revised June 2005 74VCX16373 Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs General Description The VCX16373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applica- tions. The device is byte controlled. The flip-flops appear to be transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state. The 74VCX16373 is designed for low voltage (1.2V to 3.6V) VCC applications with I/O compatibility up to 3.6V. The 74VCX16373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain- ing low CMOS power dissipation. Features s 1.2V to 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD (In to On) 3.0 ns max for 3.0V to 3.6V VCC s Power-off high impedance inputs and outputs s Support live insertion and withdrawal (Note 1) s Static Drive (IOH/IOL) r24 mA @ 3.0V VCC s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 300 mA s ESD performance: Human body model ! 2000V Machine model ! 200V s Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Note 2: Ordering Code “G” indicates Trays. Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Order Number Package Number Package Description 74VCX16373G (Note 2)(Note 3) BGA54A (Preliminary) 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 74VCX16373MTD (Note 3) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide |
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