March 1998

Revised April 1999

© 1999 Fairchild Semiconductor Corporation

DS500132.prf

www.fairchildsemi.com

74VCX16841

Low Voltage 20-Bit Transparent Latch with 3.6V Tolerant

Inputs and Outputs

General Description

The VCX16841 contains twenty non-inverting latches with

3-STATE outputs and is intended for bus oriented applica-

tions. The device is byte controlled. The flip-flops appear

transparent to the data when the Latch enable (LE) is

HIGH. When LE is LOW, the data that meets the setup time

is latched. Data appears on the bus when the Output

Enable (OE) is LOW. When OE is HIGH, the outputs are in

a high impedance state.

The 74VCX16841 is designed for low voltage (1.65V to

The 74VCX16841 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Features

s 3.6V tolerant inputs and outputs

s Power-off high impedance inputs and outputs

s Supports live insertion and withdrawal (Note 1)

±24 mA @ 3.0V V

CC

±18 mA @ 2.3V V

CC

±6 mA @ 1.65V V

CC

s Uses patented noise/EMI reduction circuitry

s Latch-up performance exceeds 300 mA

s ESD performance:

Human body model

> 2000V

Machine model

> 200V

Note 1: To ensure the high-impedance state during power up or power

value of the resistor is determined by the current-sourcing capability of the

driver.

Ordering Code:

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Pin Descriptions

Order Number

Package Number

Package Description

74VCX16841MTD

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Pin Names

Description

Output Enable Input (Active LOW)

Latch Enable Input

Inputs

Outputs