Datenblatt-Suchmaschine für elektronische Bauteile |
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CD40174BCN Datenblatt(PDF) 4 Page - Fairchild Semiconductor |
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CD40174BCN Datenblatt(HTML) 4 Page - Fairchild Semiconductor |
4 / 7 page www.fairchildsemi.com 4 AC Electrical Characteristics (Note 5) TA = 25°C, CL = 50 pF, RL = 200k and tr = tf = 20 ns, unless otherwise specified Note 5: AC Parameters are guaranteed by DC correlated testing. Note 6: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C Family Characteristics application note, AN-90. Symbol Parameter Conditions Min Typ Max Units tPHL, tPLH Propagation Delay Time to a VDD = 5V 190 300 ns Logical “0” or Logical “1” from VDD = 10V 75 110 ns Clock to Q or Q (CD40175 Only) VDD = 15V 60 90 ns tPHL Propagation Delay Time to a VDD = 5V 180 300 ns Logical “0” from Clear to Q VDD = 10V 70 110 ns VDD = 15V 60 90 ns tPLH Propagation Delay Time to a Logical VDD = 5V 230 400 ns “1” from Clear to Q (CD40175 Only) VDD = 10V 90 150 ns VDD = 15V 75 120 ns tSU Time Prior to Clock Pulse that VDD = 5V 45 100 ns Data must be Present VDD = 10V 15 40 ns VDD = 15V 13 35 ns tH Time after Clock Pulse that VDD = 5V −11 0 ns Data Must be Held VDD = 10V −40 ns VDD = 15V −30 ns tTHL, tTLH Transition Time VDD = 5V 100 200 ns VDD = 10V 50 100 ns VDD = 15V 40 80 ns tWH, tWL Minimum Clock Pulse Width VDD = 5V 130 250 ns VDD = 10V 45 100 ns VDD = 15V 40 80 ns tWL Minimum Clear Pulse Width VDD = 5V 120 250 ns VDD = 10V 45 100 ns VDD = 15V 40 80 ns tRCL Maximum Clock Rise Time VDD = 5V 15 µs VDD = 10V 5.0 µs VDD = 15V 5.0 µs tfCL Maximum Clock Fall Time VDD = 5V 15 50 µs VDD = 10V 5.0 50 µs VDD = 15V 5.0 50 µs fCL Maximum Clock Frequency VDD = 5V 2.0 3.5 MHz VDD = 10V 5.0 10 MHz VDD = 15V 6.0 12 MHz CIN Input Capacitance Clear Input 10 15 pF Other Input 5.0 7.5 pF CPD Power Dissipation Per Package (Note 6) 130 pF |
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Ähnliche Beschreibung - CD40174BCN |
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