Datenblatt-Suchmaschine für elektronische Bauteile |
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DM74LS503N Datenblatt(PDF) 1 Page - Fairchild Semiconductor |
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DM74LS503N Datenblatt(HTML) 1 Page - Fairchild Semiconductor |
1 / 4 page © 2000 Fairchild Semiconductor Corporation DS010190 www.fairchildsemi.com March 1989 Revised March 2000 DM74LS503 8-Bit Successive Approximation Register (with Expansion Control) General Description The DM74LS503 register has an active LOW Enable (E) input that is used in cascading two or more packages for longer word lengths. A HIGH signal on E, after a START operation, forces Q7 HIGH and prevents the device from accepting serial data. With the E input of an DM74LS503 connected to the CC output of a preceding (more signifi- cant) device, the DM74LS503 will be inhibited until the pre- ceding device is filled, causing its CC output to go LOW. This LOW signal then enables the DM74LS503 to accept the serial data on subsequent clocks. Features s Performs serial-to-parallel conversion s Expansion control for longer words s Storage and control for successive approximation A to D conversion s Low power Schottky version of 2503 Ordering Code: Connection Diagram Logic Symbol VCC = Pin 16 GND = Pin 8 Pin Descriptions Order Number Package Number Package Description DM74LS503N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Pin Names Description D Serial Data Input S Start Input (Active LOW) CP Clock Pulse Input (Active Rising Edge) E Conversion Enable Input (Active LOW) CC Conversion Complete Output (Active LOW) Q0–Q7 Parallel Register Outputs Q7 Complement of Q7 Output |
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