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ADM1232ARNZ-REEL71 Datenblatt(PDF) 6 Page - Analog Devices

Teilenummer ADM1232ARNZ-REEL71
Bauteilbeschribung  Microprocessor Supervisory Circuit
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ADM1232
Rev. C | Page 6 of
12
CIRCUIT INFORMATION
PB RESET
STROBE TIMEOUT SELECTION
The PB RESET input makes it possible to manually reset a
system using either a standard push-button switch or a logic
low input. An internal debounce circuit provides glitch
immunity when used with a switch, reducing the effects of
glitches on the line. The debounce circuit is guaranteed to cause
the ADM1232 to assert a reset if PB RESET is brought low for
more than 20 ms and is guaranteed to ignore low inputs of less
than 1 ms.
TD (time delay) set is used to set the strobe timeout period. The
strobe timeout period is the maximum time between high-to-
low transitions that STROBE accepts before a reset is asserted
(see
). The strobe timeout settings are listed in
.
Figure 8
Table 5
Table 5. Strobe Timeout Settings
Condition
Min
Typ
Max
Unit
TD = 0 V
62.5
150
250
ms
TD = Floating
250
600
1000
ms
TD = VCC
500
1200
2000
ms
MICROPROCESSOR
GND
TOLERANCE
RESET
STROBE
RESET
PB RESET
I/O
ADM1232
VCC
VCC
TD
STROBE
PULSE WIDTH
STROBE TIMEOUT PERIOD
STROBE
RESET
Figure 8. STROBE Parameters
Figure 6. Typical Push-Button Reset Application
RESET
PB RESET
VIL
RESET ACTIVE
TIME
PB RESET
DELAY
PB RESET TIME
VIH
5V
VCC
RESET
5V
4.5V (5% TRIP POINT)
RESET OUTPUT DELAY
HEN VCC IS FALLING
RESET OUTPUT DELAY
WHEN VCC IS RISING
W
4.25V (10% TRIP POINT)
RESET
Figure 9. Reset Output Delay
TOLERANCE
Figure 7. PB RESET
The TOLERANCE input is used to determine the level at which
VCC can vary below 5 V without the ADM1232 asserting a reset.
Connecting TOLERANCE to GND selects a −5% tolerance level
and causes the ADM1232 to generate a reset if VCC falls below
4.75 V. If TOLERANCE is connected to VCC, a −10% tolerance
level is selected, which causes the ADM1232 to generate a reset
if VCC falls below 4.5 V. See the parameters for the VCC trip point
in the Specifications section for more information.
RESET AND RESET OUTPUTS
RESET is capable of sourcing and sinking current, whereas
RESET is an open-drain MOSFET that sinks current only.
Therefore, it is necessary to pull this output high.


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