Data Sheet

AD5452W

Rev. 0 | Page 7 of 24

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No

Mnemonic

Description

1

I

DAC Current Output.

2

GND

Ground Pin.

3

SCLK

Serial Clock Input. By default, data is clocked into the input shift register upon the falling edge

of the serial clock input. Alternatively, by means of the serial control bits, the device can be

configured such that data is clocked into the shift register upon the rising edge of SCLK.

4

SDIN

Serial Data Input. Data is clocked into the 16-bit input register upon the active edge of the serial

clock input. By default, in power-up mode data is clocked into the shift register upon the falling

edge of SCLK. The control bits allow the user to change the active edge to a rising edge.

5

SYNC

Active Low Control Input. This is the frame synchronization signal for the input data. Data is

loaded to the shift register upon the active edge of the following clocks.

6

V

DD

Positive Power Supply Input. These parts can operate from a supply of 2.5 V to 5.5 V.

7

V

REF

DAC Reference Voltage Input.

8

R

FB

DAC Feedback Resistor. Establish voltage output for the DAC by connecting to external

amplifier output.

GND

SCLK

SDIN

SYNC

AD5452W

TOP VIEW

(Not to Scale)

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