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AD9958 Datenblatt(PDF) 1 Page - Analog Devices |
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AD9958 Datenblatt(HTML) 1 Page - Analog Devices |
1 / 3 page Circuit Note CN-0109 Circuit Designs Using Analog Devices Products Apply these product pairings quickly and with confidence. For more information and/or support call 1-800-AnalogD (1-800-262-5643) or visit www.analog.com/circuit. Devices Connected/Referenced AD9958/ AD9858 500 MSPS/1 GSPS Direct Digital Synthesizer (DDS) AD9515 Clock Distribution IC and Pin Programmable Mini-Divider AD6645 14-Bit, 80 MSPS/105 MSPS ADC Low Jitter Sampling Clock Generator for High Performance ADCs Using the AD9958/AD9858 500 MSPS/1GSPS DDS and AD9515 Clock Distribution IC Rev. 0 “Circuits from the Lab” from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of eachcircuit,andtheirfunctionandperformance havebeentestedandverifiedinalabenvironment atroomtemperature.However,youaresolelyresponsible fortestingthe circuit anddetermining its suitability and applicability for your use and application. Accordingly, in no event shall Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to anycausewhatsoeverconnectedtotheuseofany“CircuitfromtheLab”. (Continuedonlastpage) One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. CIRCUIT FUNCTION AND BENEFITS This circuit uses a direct digital synthesizer (DDS) with sub- Hertz tuning resolution as a low jitter sampling clock source for high performance ADCs. The AD9515 clock distribution IC provides PECL logic levels to the ADC. However, the AD9515 internal divider feature also allows the DDS to run at a higher frequency into the AD9515 front end, effectively increasing input slew rate. A higher slew rate into the AD9515 input squaring circuit can help reduce broadband jitter in the clock path. Jitter on the ADC sampling clock produces degradation in the overall signal-to-noise ratio (SNR). The relationship is given by Equation 1. = j ft SNR π 2 1 log 20 10 (1) where f is the full-scale analog input frequency, and tj is the rms jitter. "SNR" in Equation 1 is the SNR due solely to clock jitter and does not depend on the resolution of the ADC. The following data supports low jitter attainable from a DDS in clocking applications. Further details on Equation 1 and its use for evaluating the jitter on ADC sampling clocks can be found in Application Note AN-501. CIRCUIT DESCRIPTION The circuit configuration in Figure 1 shows a DDS-based clock generator, consisting of a DDS followed by a reconstruction filter and an AD9515 clock distribution IC, used to provide the sampling clock for an analog-to-digital converter (ADC). The DDS sampling clock is derived from a Rohde and Schwarz SMA signal generator. The jitter measurement was made by using the clock derived from the DDS and the AD9515 as the sampling clock for the high performance AD6645 14-bit, 80 MSPS/105 MSPS ADC. The analog input signal for the ADC is a filtered 170.3 MHz sine wave derived from a low jitter Wenzel crystal oscillator (www.wenzel.com). Data was taken on two different DDSes: the AD9958 (500 MSPS) and the AD9858 (1 GSPS). AD6645 FFT ANALYSIS BPF ROHDE AND SCHWARZ SMA GENERATOR 500MHz AND 1GHz @ +6dBm RECONSTRUCTION FILTER AIN = 170.3MHz DIFFERENTIAL PECL SAMPLING CLOCK WENZEL ULN-SERIES CRYSTAL OSCILLATOR AD9515 LPF/BPF DDS AD9958, AD9858 Figure 1. DDS-Based ADC Sampling Clock Generator (Simplified Diagram) By evaluating the contribution of the ADC’s differential non- linearity and thermal noise and then applying the DDS-based clock and measuring the ADC SNR, the added jitter attributable to the DDS-based clock can be derived. For more details on the measurement setup and the jitter calculations, refer to Application Note AN-823. Also, Application Note AN-837 is instructive for designing DAC reconstruction filters with optimal stop-band performance. Table 1 shows data for the AD9958 test results. The data confirms that better jitter performance is achieved as the frequency, or slew rate, of the DDS output frequency is increased and as the DDS output filter pass band is decreased. Table 2 shows the AD9858 with a 5% band-pass filter, a 225 MHz low-pass filter, and various levels of DDS output power. As expected, lower jitter is achieved as power is increased and bandwidth reduced. With a 5% band-pass filter, the majority of the spurs from the DAC are attenuated. The jitter in this case is much more dependent on noise coupling between the DAC output and the limiter input. This is proven by the strong correlation between jitter reduction and increased |
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Ähnliche Beschreibung - AD9958 |
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