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AD5629R Datenblatt(PDF) 7 Page - Analog Devices

Teilenummer AD5629R
Bauteilbeschribung  Octal, 12-/16-Bit, I2C, denseDACs with 5 ppm/째C On-Chip Reference
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Hersteller  AD [Analog Devices]
Direct Link  http://www.analog.com
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Data Sheet
AD5629R/AD5669R
Rev. B | Page 7 of 32
I2C TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 400 kHz, unless otherwise noted.
Table 4.
Parameter
Conditions
Min
Max
Unit
Description
fSCL1
Standard mode
100
kHz
Serial clock frequency
Fast mode
400
kHz
t1
Standard mode
4
μs
tHIGH, SCL high time
Fast mode
0.6
μs
t2
Standard mode
4.7
μs
tLOW, SCL low time
Fast mode
1.3
μs
t3
Standard mode
250
ns
tSU;DAT, data setup time
Fast mode
100
ns
t4
Standard mode
0
3.45
μs
tHD;DAT, data hold time
Fast mode
0
0.9
μs
t5
Standard mode
4.7
μs
tSU;STA, setup time for a repeated start condition
Fast mode
0.6
μs
t6
Standard mode
4
μs
tHD;STA, hold time (repeated) start condition
Fast mode
0.6
μs
t7
Standard mode
4.7
μs
tBUF, bus-free time between a stop and a start condition
Fast mode
1.3
μs
t8
Standard mode
4
μs
tSU;STO, setup time for a stop condition
Fast mode
0.6
μs
t9
Standard mode
1000
ns
tRDA, rise time of SDA signal
Fast mode
300
ns
t10
Standard mode
300
ns
tFDA, fall time of SDA signal
Fast mode
300
ns
t11
Standard mode
1000
ns
tRCL, rise time of SCL signal
Fast mode
300
ns
t11A
Standard mode
1000
ns
tRCL1, rise time of SCL signal after a repeated start condition and
after an acknowledge bit
Fast mode
300
ns
t12
Standard mode
300
ns
tFCL, fall time of SCL signal
Fast mode
300
ns
t13
Standard mode
10
ns
LDAC pulse width low
Fast mode
10
ns
t14
Standard mode
300
ns
Falling edge of ninth SCL clock pulse of last byte of a valid write to
the LDAC falling edge
Fast mode
300
ns
t15
Standard mode
20
ns
CLR pulse width low
Fast mode
20
ns
tSP 2
Fast mode
0
50
ns
Pulse width of spike suppressed
1
The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on the EMC
behavior of the part.
2
Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or less than 10 ns for high speed mode.


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