Datenblatt-Suchmaschine für elektronische Bauteile |
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TL16C754BPNG4 Datenblatt(PDF) 9 Page - Texas Instruments |
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TL16C754BPNG4 Datenblatt(HTML) 9 Page - Texas Instruments |
9 / 40 page TL16C754B QUAD UART WITH 64BYTE FIFO SLLS397A − NOVEMBER 1999 − REVISED JUNE 2004 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional description (continued) The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an ordinary byte from the FIFO. This means that even if the word length is set to be 5, 6, or 7 characters then the 5, 6, or 7 least significant bits of Xoff1,2/Xon1,2 will be transmitted. The transmission of 5, 6, or 7 bits of a character is seldom done, but this functionality is included to maintain compatibility with earlier designs. It is assumed that software flow control and hardware flow control will never be enabled simultaneously. Figure 4 shows a software flow control example. UART 1 Parallel to Serial Serial to Parallel Xon-1 Word Xon-2 Word Xoff-1 Word Xoff-1 Word Transmit FIFO Serial to Parallel Parallel to Serial Xon-1 Word Xon-2 Word Xoff-1 Word Xoff-2 Word Receive FIFO Data Xoff − Xon − Xoff Compare Programmed Xon−Xoff Characters UART 2 Figure 4. Software Flow Control Example software flow control example Assumptions: UART1 is transmitting a large text file to UART2. Both UARTs are using software flow control with single character Xoff (0F) and Xon (0D) tokens. Both have Xoff threshold (TCR [3:0]=F) set to 60 and Xon threshold (TCR[7:4]=8) set to 32. Both have the interrupt receive threshold (TLR[7:4]=D) set to 52. UART1 begins transmission and sends 52 characters, at which point UART2 will generate an interrupt to its processor to service the RCV FIFO, but assume the interrupt latency is fairly long. UART1 will continue sending characters until a total of 60 characters have been sent. At this time UART2 will transmit a 0F to UART1, informing UART1 to halt transmission. UART1 will likely send the 61st character while UART2 is sending the Xoff character. Now UART2 is serviced and the processor reads enough data out of the RCV FIFO that the level drops to 32. UART2 will now send a 0D to UART1, informing UART1 to resume transmission. |
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