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AD5165EVAL Datenblatt(PDF) 3 Page - Analog Devices |
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AD5165EVAL Datenblatt(HTML) 3 Page - Analog Devices |
3 / 16 page AD5165 Rev. 0 | Page 3 of 16 ELECTRICAL CHARACTERISTICS—100 kΩ VERSION VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted. Table 1. Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect −1 ±0.1 +1 LSB Resistor Integral Nonlinearity2 R-INL RWB, VA = no connect −2 ±0.25 +2 LSB Nominal Resistor Tolerance3 ∆RAB/RAB TA = 25°C −20 +20 % Resistance Temperature Coefficient (∆RAB/RAB)/∆Tx106 VAB = VDD, wiper = no connect 35 ppm/°C Wiper Resistance RW VDD = 2.7 V/5.5 V 85/50 150/120 Ω DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Resolution N 8 Bits Differential Nonlinearity4 DNL −1 ±0.1 +1 LSB Integral Nonlinearity4 INL −1 ±0.3 +1 LSB Voltage Divider Temperature Coefficient (∆VW/VW )/∆Tx106 Code = 0x80 15 ppm/°C Full-Scale Error VWFSE Code = 0xFF −0.5 −0.3 0 LSB Zero-Scale Error VWZSE Code = 0x00 0 0.1 0.5 LSB RESISTOR TERMINALS Voltage Range5 VA,B,W GND VDD V Capacitance6 A, B CA,B f = 1 MHz, measured to GND, Code = 0x80 90 pF Capacitance6 W CW f = 1 MHz, measured to GND, Code = 0x80 95 pF Common-Mode Leakage ICM VA = VB = VDD/2 1 nA DIGITAL INPUTS AND OUTPUTS Input Logic High VIH VDD = 2.7 V to 5.5 V 1.8 V Input Logic Low VIL VDD = 2.7 V to 5.5 V 0.6 V Input Capacitance6 CIL 5 pF POWER SUPPLIES Power Supply Range VDD RANGE 2.7 5.5 V Supply Current IDD Digital inputs = 0 V or VDD 0.05 1 µA VDD = 2.7 V, digital inputs = 1.8 V 10 µA VDD = 5 V, digital inputs = 1.8 V 500 µA Power Dissipation7 PDISS Digital inputs = 0 V or VDD 5.5 µW Power Supply Sensitivity PSS VDD = +5 V ± 10%, Code = Midscale ±0.001 ±0.005 %/% DYNAMIC CHARACTERISTICS6, 8 Bandwidth −3 dB BW Code = 0x80 55 kHz Total Harmonic Distortion THDW VA =1 V rms, VB = 0 V, f = 1 kHz, 0.05 % VW Settling Time tS VA = 5 V, VB = 0 V, ±1 LSB error band 2 µs Resistor Noise Voltage Density eN_WB RWB = 50 kΩ 28 nV/√Hz 1 Typical specifications represent average readings at +25°C and VDD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 VAB = VDD, wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. 5 Resistor terminals A, B, and W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 8 All dynamic characteristics use VDD = 5 V. |
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