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MC146805E2CFN Datenblatt(PDF) 7 Page - InnovASIC, Inc |
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MC146805E2CFN Datenblatt(HTML) 7 Page - InnovASIC, Inc |
7 / 33 page IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 Functional Description Memory: The MPU is capable of addressing 8192 bytes of memory and I/O registers. The locations are divided into internal memory space and external memory space as shown in Figure 5. The first 128 bytes of memory contain internal port I/O locations, timer locations, and 112 bytes of RAM. The MPU can read from or write to any of these locations. During program reads from on chip locations, the MPU accepts data only from the addressed on chip location. Any read data appearing on the input bus is ignored. The shared stack area is used during interrupts or subroutine calls. A maximum of 64 bytes of RAM is available for stack usage. The stack pointer is set to $7f at power up. The unused bytes of the stack can be used for data storage or temporary work locations, but care must be taken to prevent it from being overwritten due to stacking from an interrupt or subroutine call. RAM (112 BYTES) I/O PORTS TIMER RAM EXTERNAL MEMORY SPACE (8064 BYTES) TIMER INTERRUPT FROM WAIT STATE ONLY TIMER INTERRUPT EXTERNAL INTERRUPT SWI RESET PORT A DATA REGISTER PORT B DATA REGISTER EXTERNAL MEMORY SPACE EXTERNAL MEMORY SPACE PORT A DATA DIRECTION REGISTER PORT B DATA DIRECTION REGISTER EXTERNAL MEMORY SPACE EXTERNAL MEMORY SPACE TIMER DATA REGISTER TIMER CONTROL REGISTER EXTERNAL MEMORY SPACE $1FF6 - $1FF7 $1FF8 - $1FF9 $1FFA - $1FFB $1FFC - $1FFD $1FFE - $1FFF $0000 $007F $0080 $00FF $0100 63 64 127 0 127 128 255 256 8191 INTERRUPT VECTORS ACCESS VIA PAGE 0 DIRECT ADDRESS STACK (64 BYTES MAX) 0 1 2 3 4 5 6 7 8 9 10 15 16 Figure 5. Memory Map Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Page 7 of 33 1-888-824-4184 © |
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