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AK61584 Datenblatt(PDF) 16 Page - Asahi Kasei Microsystems |
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AK61584 Datenblatt(HTML) 16 Page - Asahi Kasei Microsystems |
16 / 38 page ASAHI KASEI [AK61584] 0185-E-00 98/04 -16- When the jitter attenuator is in the receive path, upon loss of signal, the frequency of last recovered signal is held over. When the jitter attenuator is not in the re- ceive path, the last recovered frequency is not held over, Rather, the output frequency will become the frequen- cy of the reference clock. Any time a channel is reset or powered down, (for example by RESET, PD1, PD2, or power-on reset), the loss of signal indicator on that channel is set high. The loss of signal indicator remains high until data is recovered by the receiver. Receiver AIS Detection The receiver detects AIS upon observation of 99.9% ones density for 5.3 ms. More specifically, the AIS detection criteria is less than 9 zeros out of 8192 bits. When AIS is detected, the AK61584 sets the control register bits AIS and Latched-AIS, high. In the coder mode, the receiver also sets output pin AIS high. The end of the AIS condition occurs when > 9 zeros are detected out of 8192 bits. The AIS bits in the status register operate the same as the LOS bits (see Ta- ble5) upon detecting AIS. When a channel is powered down, all indications are forced low. JITTER ATTENUATOR The jitter attenuator can be switched into either the receive or transmit paths. Alternatively it can be removed from both paths (thereby decreasing propagation delay). Atten0x Atten1x Location of Jitter Attenuator 0 0 Receiver 0 1 Transmitter 1 0 Neither 1 1 Reserved Table 4. Jitter Attenuation Control In hardware mode, the location of the attenuators is the same for channel 1 and 2, and is controlled by pins ATTEN0 and ATTEN1. See Table4. In host modes, Figure 13. Typical Jitter Transfer Function the location of the attenuators is programmable on a per-channel basis, using bits ATTEN01 and ATTEN11 for channel 1, and bits ATTEN02 and ATTEN12 for channel 2. The control bits also conform to Table 4. A typical jitter attenuation curve is shown in Figure 13. The attenuator consists of a 64-bit FIFO, a nar- row-band monolithic PLL, and control logic. Signal jitter is absorbed in the FIFO. The FIFO is designed to neither overflow nor underflow. If overflow or under- flow is imminent, the jitter transfer function is altered to insure that no bit errors occur. Under this circumstance, jit- ter gain may occur, and jitter should be attenuated exter- nally in a frame buffer. The jitter attenuator will typi- cally tolerate 43 UIs before the overflow/underflow mechanism takes effect. Before the jitter attenuator has had time to “lock” to the average incoming frequency, for example, after a chip reset, the attenuator will tolerate a minimum of 22 UIs before the overflow/underflow mechanism takes effect. For T1/E1 line cards employed in high-speed mul- tiplexers (e.g.,SONET and SDH), the jitter attenu- ator is typically used in the transmit path. The attenuator can be fed a gapped transmit clock, with gaps 22 UIs, and transmit clock burst rate <8 MHz. |
Ähnliche Teilenummer - AK61584 |
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Ähnliche Beschreibung - AK61584 |
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