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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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AK61584 Datenblatt(PDF) 17 Page - Asahi Kasei Microsystems |
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AK61584 Datenblatt(HTML) 17 Page - Asahi Kasei Microsystems |
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17 / 38 page  ASAHI KASEI [AK61584] 0185-E-00 98/04 -17- CODER MODE In the coder Mode, three line codes are available: AMI, B8ZS and HDB3. The input to the encoder is TDATA. The outputs from the decoder are RDATA and BPV (Bipolar Violation Strobe). In host modes, the encoder and decoder are selected using control register bits CODER (1 =coder active, 0 = transparent mode, coder disabled) and AMI-T/AMI-R (1 =AMI, 0 =B8ZS or HDB3) where the transmitter and receiver can be inde- pendently controlled. The selection of B8ZS versus HDB3 is made by the control bits: CON<0:3>. In hardware mode, the encoder and decoder are controlled simultaneously by pins CODER1 and CODER2 (1 =coder active, 0 =transparent mode, coder disable). The line code is B8ZS or HDB3. The selection of B8ZS versus HDB3 is made by the pins: CON<0:2>. In the coder mode, the receiver sets output pins AIS1 and AIS2 high, when AIS is detected, respectively on channels 1 and 2. In the coder mode, pin BPV goes to a logic 1 for one bit period when a bipolar violation is detected in the received signal. B8ZS (or HDB3) zero substitutions are not flagged as bipolar violations if the B8ZS (or HDB3) decoder has been enabled. A latched-BPV indica- tion is also available in the status register. REFERENCE CLOCK The AK61584 requires a T1 or E1 reference clock. This clock is input on pin REFCLK, and can be either a 1-X clock (i.e.,1.544 MHz or 2.048 MHz), or a 8-X clock (i.e.,12.352 MHz or 16.384 MHz). pin 1XCLK determines which option is used (active high for 1-X, and low for 8-X). Any jitter present on the reference clock will not be filtered by the jitter attenuator, and will be present on the output of the jitter attenuator. The reference clock should have a minimum accuracy of 100 ppm. LOOPBACKS Local Loopbacks The two local loopbacks take clock and data presented on TCLK, TPOS, and TNEG, or TDATA and out- puts it at RCLK, RPOS and RNEG, or RDATA. As shown in the block diagram on the first page of the data sheet, loopback 1 includes the jitter attenuator. Loop- back 2 includes the line driver and the receiver. For both local loopbacks, inputs to the transmitter are still transmitted on the line, unless TAOS has been se- lected in which case, AMI-coded continuous ones are transmitted to the line at the rate determined by TCLK. Receiver inputs are ignored when local loopback is in effect. Local loopback 1 is selected by a control pin, or a control bit. Loopback 2 is selected only via a con- trol bit. Remote Loopback In remote loopback, the recovered clock and data input on RTIP and RRING are sent back out on the line via TTIP and TRING as shown in the block diagram on the front page of this data sheet. The recovered in- coming signals are also sent to RCLK, RPOS and RNEG, or RDATA. A remote loopback may be selected in both the hardware and host modes. Simultaneous selec- tion of local and remote loopback modes is not valid. POWER DOWN The PD1 and PD2 pins reset, respectively, the trans- mitter, receiver and jitter attenuator of channels 1 and 2. Whenever PD1 or PD2 is selected, the selected channel remains powered down, and the outputs (pins RCLK, RPOS, RNEG, RDATA, BPV, AIS, TTIP, and TRING) associated with that channel are put into a high-impedance state, and pin LOS is set high. Addi- tionally, the status register bits are reset. The control, mask, and arbitrary waveform registers are unchanged. |
Ähnliche Teilenummer - AK61584 |
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Ähnliche Beschreibung - AK61584 |
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