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LM2512ASNX Datenblatt(PDF) 11 Page - Texas Instruments

Teilenummer LM2512ASNX
Bauteilbeschribung  LM2512A Mobile Pixel Link (MPL-1), 24 Bit RGB Display Interface Serializer with Optional Dithering and Look Up Table
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Hersteller  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

LM2512ASNX Datenblatt(HTML) 11 Page - Texas Instruments

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R0
R1
R4
R5
B0
B1
B4
B5
R0
R2
R3
B2
B3
F0
F1
R2
MC
MD1
MD2
G0
G1
G4
G5
G2
G3
DE
PE
VS
HS
R0
R1
G0
G1
VS
HS
R0
R2
R3
DE
PE
R2
MC
MD0
MD1
G2
G3
B2
B3
B0
B1
R4
R5
F0
F1
R4
MD2
G4
G5
B4
B5
LM2512A
www.ti.com
SNLS269B – AUGUST 2007 – REVISED MAY 2013
Figure 11. 24-bit to 18-bit Dithered, 3 MD Lane, RGB Transaction
Figure 12. 24-bit to 18-bit Dithered, 2 MD Lane (Default), RGB Transaction (NOTE MD1 and MD2)
Serial Payload Parity Bit
Odd Parity is calculated on the RGB bits, control (VS, HS, and DE) bits and F0, F1 bits and then sent from the
SER to the DES via the serial PE bit. This is included for compatibility with certain MPL Deserializers.
Synchronization Detect and Recovery
If a data error or clock slip error occurs over the MPL link, the RGB MPL Deserializer can detect this condition
and recover from it. The method chosen is a data transparent method, and has very little overhead because it
does not use a data expansion coding method. For the Dithered 18-bit color transaction, it uses two bits that are
already required in the 4 MC cycle transaction. Total overhead for each pixel is 3/24 or 12.5%.
The LM2512A MPL RGB Serializer simply increments the two bit field F[1:0] on every pixel (MPL frame)
transmitted. Therefore every four MPL frames, the pattern will repeat. It is very unlikely that this pattern would be
found within the payload data, and if it were found, the probability that it would repeat for many frames becomes
infinitely small. This code is used by the MPL Deserializer to detect any frame alignment problems and quickly
recover.
The RGB MPL Deserializer, upon a normal power up sequence, starts in the proper synchronization. If
synchronization is lost for any reason, it searches for the incrementing pattern. Once found, it resynchronizes the
output pixel data and timing signals. See MPL DES Datasheet for details on how the specific DES handles the
Frame Sequence.
OPTIONAL DITHERING FEATURE
The LM2512A is a 2 or 3-Lane MPL Serializer, 24-bit RGB input data (8-bits/color channel) is internally dithered
to 18-bits (6-bits/color channel) using a high-quality stochastic dithering process. This process has a "blue noise"
characteristic that minimizes the visibility of the dither patterns. The resulting data stream of 18-bit data is then
serialized and transmitted via MPL.
The Dither circuitry requires the VS control signal for proper operation. This signal is used to generate a
internal signal that marks the start of the (video) frame. The serializer samples and sends the VS information
unmodified.
Dithering parameters are controled by two registers. When the dithering is bypassed, only RGB[7:2] is serialized
and transmitted for 18-bit input RGB [5:0] (MSB aligned). RGB[1:0] should not be connected and the unsed input
should be tied low; do not leave input open.
Copyright © 2007–2013, Texas Instruments Incorporated
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